fir3.mdl

用DSP BUILDER设计的3阶和四阶滤波器

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      SourceBlock	      "bus_alteradspbuilder/Output"
      SourceType	      "AltBus AlteraBlockSet"
      sgn		      "Signed Integer"
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"ctor"
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      Inputs		      "4"
      direction		      "++++"
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	axes1			"%<SignalLabel>"
	axes2			"%<SignalLabel>"
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      family		      "Stratix"
      opt		      "Balanced"
      synthtool		      "Others"
      vstim		      on
      SynthAct		      "None"
      workdir		      "g:\\MATLAB701\\work"
      Procetype		      "prod"
      UseReset		      on
      ResetPin		      "Active High"
      ClockPin		      "Output to Pin"
      ClockPeriod	      "20"
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      CreatePtfFile	      off
      SignalTapDepth	      "128"
      VerilogSupport	      off
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      JTAGCable		      "USB-Blaster [USB-0]"
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