📄 fir4.mdl
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sgn "Signed Integer"
nodetype "Input Port"
bwl "9"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "Input1"
ppat "g:\\MATLAB701\\work\\DSPBuilder_fir4"
nSgCpl "1"
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bwl "9"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
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cst "0"
modulename "Input2"
ppat "g:\\MATLAB701\\work\\DSPBuilder_fir4"
nSgCpl "1"
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bp off
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ppat "g:\\MATLAB701\\work\\DSPBuilder_fir4"
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bwl "9"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
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ppat "g:\\MATLAB701\\work\\DSPBuilder_fir4"
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sgn "Signed Integer"
nodetype "Output Port"
bwl "9"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "Output"
nSgCpl "0"
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ForegroundColor "blue"
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SourceType "Sum AlteraBlockSet"
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direction "+"
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pipeline "0"
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family "Stratix"
opt "Balanced"
synthtool "Others"
vstim on
SynthAct "None"
workdir "g:\\MATLAB701\\work"
Procetype "prod"
UseReset on
ResetPin "Active High"
ClockPin "Output to Pin"
ClockPeriod "20"
UseSignalTap off
CreatePtfFile off
SignalTapDepth "128"
VerilogSupport off
UniqueVHDLHierarchyName off
RegenerateIPFunctionalModel off
RunUpdatedSimulation off
JTAGCable "USB-Blaster [USB-0]"
dspb_ver "5.1"
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sgn "Signed Integer"
nodetype "Input Port"
bwl "9"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "xin"
ppat "g:\\MATLAB701\\work\\DSPBuilder_fir4"
nSgCpl "1"
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SrcPort 1
Points [315, 0]
DstBlock "Product3"
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SrcBlock "Input3"
SrcPort 1
Points [285, 0]
DstBlock "Product2"
DstPort 2
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SrcPort 1
Points [55, 0; 0, 110]
DstBlock "Parallel \nAdder Subtractor"
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Points [60, 0; 0, 5]
DstBlock "Parallel \nAdder Subtractor"
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Points [55, 0; 0, -80]
DstBlock "Parallel \nAdder Subtractor"
DstPort 3
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SrcBlock "Product3"
SrcPort 1
Points [45, 0; 0, -175]
DstBlock "Parallel \nAdder Subtractor"
DstPort 4
}
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SrcBlock "Parallel \nAdder Subtractor"
SrcPort 1
DstBlock "Output1"
DstPort 1
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