main.c

富士通单片机MB902420系列 extINT Project: All external Interrupt-Pins INT0 .. INT7 will be enabled. A fall

/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */
/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
/* ELIGIBILITY FOR ANY PURPOSES.                                             */
/*                 (C) Fujitsu Microelectronics Europe GmbH                  */

/*---------------------------------------------------------------------------
  MAIN.C
  - description
  - See README.TXT for project description and disclaimer.

/*---------------------------------------------------------------------------*/

#include "mb90425.h"

/* Note:
   The -A and -B versions include a CPU Detection Reset Circuit. 
   This must be cleared periodically to prevent program reset.

   The conditions for clearing the counter of this circuit are given below:
   1. Writing 0 to CL bit of LVRC register
   2. Internal reset
   3. Stopping main oscillation clock
   4. Transition to sleep mode
   5. Transition to time-base timer mode or timer mode
   6. Starting hold
*/

void clear_CPU_operation_detection (void)
{
 LVRC = 0x35;	        /* clears CPU operation detection */
}

/*---------------------------------------------------------------------------
  Interrupt Handler
/*---------------------------------------------------------------------------*/    
__interrupt void extINT0 (void)
{
  PDR4_P40 = ~PDR4_P40;
  EIRR_ER0 = 0;
}

__interrupt void extINT1 (void)
{
  PDR4_P41 = ~PDR4_P41;
  EIRR_ER1 = 0;
}

__interrupt void extINT2 (void)
{
  PDR4_P42 = ~PDR4_P42;
  EIRR_ER2 = 0;
}

__interrupt void extINT3 (void)
{
  PDR4_P43 = ~PDR4_P43;
  EIRR_ER3 = 0;
}

__interrupt void extINT45 (void)
{
  if (EIRR_ER4)
  {
    PDR4_P44 = ~PDR4_P44;
    EIRR_ER4 = 0;
  }
  else
  {
    PDR4_P45 = ~PDR4_P45;
    EIRR_ER5 = 0;
  }
}

__interrupt void extINT67 (void)
{
  if (EIRR_ER6)
  {
    PDR4_P46 = ~PDR4_P46;
    EIRR_ER6 = 0;
  }
  else
  {
    PDR4_P47 = ~PDR4_P47;
    EIRR_ER7 = 0;
  }
}

/*---------------------------------------------------------------------------
  MAIN.C
/*---------------------------------------------------------------------------*/    

void main(void)
{
  InitIrqLevels();
  __set_il(7);  /* allow all levels */
  __EI();       /* globaly enable interrupts */

  PDR4 = 0xFF;  /* switch off all leds */
  DDR4 = 0xFF;  /* set parallel port direction register : output */
  
  ENIR = 0x00;  /* disable all external Interrupts */
  
  /* in order to use external Interrupts */
  /* the according I/O-Pins have to be set as inputs */
  
  DDR5_D50 = 0; /* INT 0 */
  DDR5_D51 = 0; /* INT 1 */
  DDR5_D52 = 0; /* INT 2 */
  DDR5_D53 = 0; /* INT 3 */
  
  DDR0_D00 = 0; /* INT 4 */
  DDR0_D01 = 0; /* INT 5 */
  DDR0_D02 = 0; /* INT 6 */
  DDR0_D03 = 0; /* INT 7 */
  
  /* Request level setting register: ELVRx */
  /* LBx, LAx = 00  => "L" level      is to be detected */
  /* LBx, LAx = 01  => "H" level      is to be detected */
  /* LBx, LAx = 10  => A rising  edge is to be detected */
  /* LBx, LAx = 11  => A falling edge is to be detected */
  
  ELVR_LB0 = 1; ELVR_LA0 = 1;
  ELVR_LB1 = 1; ELVR_LA1 = 1;
  ELVR_LB2 = 1; ELVR_LA2 = 1;
  ELVR_LB3 = 1; ELVR_LA3 = 1;
  ELVR_LB4 = 1; ELVR_LA4 = 1;
  ELVR_LB5 = 1; ELVR_LA5 = 1;
  ELVR_LB6 = 1; ELVR_LA6 = 1;
  ELVR_LB7 = 1; ELVR_LA7 = 1;
  
  /* clear Interrupt Cause Register */
  EIRR = 0x00;
 
  /* Interrupt Enable Register ENIRx */
  /* ENIR_ENx = 0   => disable external INTx */
  /* ENIR_ENx = 1   => enable  external INTx */
  
  ENIR_EN0 = 1;
  ENIR_EN1 = 1;
  ENIR_EN2 = 1;
  ENIR_EN3 = 1;
  ENIR_EN4 = 1;
  ENIR_EN5 = 1;
  ENIR_EN6 = 1;
  ENIR_EN7 = 1;

  
  /* Interrupt control register ICRx: */
  /* in our template-projects the ICR will be set within the module "vetor.c" */
  /* and call by InitIrqLevels() from main.c */
  
  while(1)
  {
    clear_CPU_operation_detection();
  }

}