start.lst

富士通单片机MB902420系列 CAN Project: CAN0 will work as a simple Repeater. Received data will appear at P

                                          375                                          ; be copied
                                                   from ROM to RAM
                                          376
                                          377      ; to get this option properly working the code t
                                                   o be executed has to
                                          378      ; be linked to section RAMCODE (e.g. by #pragma
                                                   section). The section
                                          379      ; RAMCODE has be located in RAM and the section
                                                   @RAMCODE has to be
                                          380      ; located at a fixed address in ROM by linker se
                                                   ttings.
                                          381
                                          382      ; <<< END OF SETTINGS >>>
                                          383
                                          384      ;===============================================
                                                   =====================
                                          385      ; 5  Section and Data Declaration
                                          386      ;===============================================
                                                   =====================
                                          387
                                          388      ;===============================================
                                                   =====================
                                          389      ; 5.1  Several fixed addresses (fixed for MB90xx
                                                   x controllers)
                                          390      ;===============================================
                                                   =====================
                                          391
          = 000000A0                      392      LPMCR     .EQU      0xA0           ; Low power m
                                                   ode control register
_____________________________________________________________________________
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STARTUP FILE FOR MEMORY INITIALISATION

SN LOC    OBJ                           LLINE      SOURCE

          = 000000A1                      393      CKSCR     .EQU      0xA1           ; Clock selec
                                                   t control register
                                          394      #if BUSMODE != SINGLE_CHIP
                                          395   X  ARSR      .EQU      0xA5           ; *1) Automat
                                                   ic ready function reg
                                          396   X  HACR      .EQU      0xA6           ; *1) Externa
                                                   l address output reg
                                          397   X  EPCR      .EQU      0xA7           ; *1) Bus con
                                                   trol signal selection
                                          398      #endif
                                          399      #if FAMILY == MB90500 || FAMILY == MB90400
          = 0000006F                      400      ROMM      .EQU      0x6F           ; *2) ROM mir
                                                   ror control register
                                          401      #endif
          = 000000A8                      402      WDTC      .EQU      0xA8           ; Watchdog co
                                                   ntrol register
          = 000000A9                      403      TBTC      .EQU      0xA9           ; Timerbase t
                                                   imer control register
                                          404
                                          405      ; *1 only for devices with external bus
                                          406      ; *2 only for MB905xx (FFMC-16LX) devices
                                          407
                                          408      ;===============================================
                                                   =====================
                                          409      ; 5.2  Declaration of __near addressed data sect
                                                   ions
                                          410      ;===============================================
                                                   =====================
                                          411
                                          412      ; sections to be cleared
DA 000000 -----------<DATA>------------   413                .SECTION  DATA,      DATA,   ALIGN=2
                                                   ; zero clear area
DI 000000 ----------<DIRDATA>----------   414                .SECTION  DIRDATA,   DIR,    ALIGN=2
                                                   ; zero clear direct
LI 000000 ----------<LIBDATA>----------   415                .SECTION  LIBDATA,   DATA,   ALIGN=2
                                                   ; zero clear lib area
                                          416
                                          417      ; sections to be initialised with start-up value
                                                   s
IN 000000 -----------<INIT>------------   418                .SECTION  INIT,      DATA,   ALIGN=2
                                                   ; initialised area
DI 000000 ----------<DIRINIT>----------   419                .SECTION  DIRINIT,   DIR,    ALIGN=2
                                                   ; initialised dir
LI 000000 ----------<LIBINIT>----------   420                .SECTION  LIBINIT,   DATA,   ALIGN=2
                                                   ; initialised lib area
                                          421      #if CONSTDATA == RAMCONST
CI 000000 -----------<CINIT>-----------   422                .SECTION  CINIT,     DATA,   ALIGN=2
                                                   ; initialised const
                                          423      #endif
                                          424
                                          425      ; sections containing start-up values for initia
                                                   lised sections above
DC 000000 ----------<DCONST>-----------   426                .SECTION  DCONST,    CONST,  ALIGN=2
                                                   ; DINIT initialisers
_____________________________________________________________________________
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STARTUP FILE FOR MEMORY INITIALISATION

SN LOC    OBJ                           LLINE      SOURCE

DI 000000 ---------<DIRCONST>----------   427                .SECTION  DIRCONST, DIRCONST,ALIGN=2
                                                   ; DIRINIT initialisers
LI 000000 ---------<LIBDCONST>---------   428                .SECTION  LIBDCONST, CONST,  ALIGN=2
                                                   ; LIBDCONST init val
                                          429
                                          430                ; following setion is either copied to
                                                    CINIT (RAMCONST) or
                                          431                ; mapped by ROM-mirror function (ROMCO
                                                   NST)
CO 000000 -----------<CONST>-----------   432                .SECTION  CONST,     CONST,  ALIGN=2
                                                   ; CINIT initialisers
                                          433
                                          434      ;===============================================
                                                   =====================
                                          435      ; 5.3  Declaration of RAMCODE section and labels
                                          436      ;===============================================
                                                   =====================
                                          437
                                          438      #if COPY_RAMCODE == ON
                                          439   X            .SECTION  RAMCODE,   CODE,  ALIGN=1
                                          440   X            .IMPORT _RAM_RAMCODE
                                                   ; provided by linker
                                          441   X            .IMPORT _ROM_RAMCODE
                                                   ; provided by linker
                                          442      #endif
                                          443
                                          444
                                          445      ;===============================================
                                                   =====================
                                          446      ; 5.4  Declaration of sections containing other
                                                   sections description
                                          447      ;===============================================
                                                   =====================
                                          448
                                          449      ; DCLEAR contains start address and size of all
                                                   sections to be cleared
                                          450      ; DTRANS contains source and destination address
                                                    and size of all
                                          451      ; sections to be initialised with start-up value
                                                   s
                                          452      ; The compiler automatically adds a descriptor f
                                                   or each __far addressed
                                          453      ; data section to DCLEAR or DTRANS. These __far
                                                   section are separated
                                          454      ; for each C-module.
                                          455
                                          456      ; In addition the start-up file adds the descrip
                                                   tors of the previously
                                          457      ; declared __near section here. This way the sam
                                                   e code in the start-up
                                          458      ; file can be used for initialising all sections
                                                   .
                                          459
DC 000000 ----------<DCLEAR>-----------   460         .SECTION  DCLEAR,    CONST,  ALIGN=2  ; zero
_____________________________________________________________________________
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STARTUP FILE FOR MEMORY INITIALISATION

SN LOC    OBJ                           LLINE      SOURCE

                                                   clear table
                                          461         ;    Address         Bank            Size
DC 000000 0000S 0000S 0000S               462         .DATA.H DATA,    BNKSEC DATA,    SIZEOF(DATA
                                                     )
DC 000006 0000S 0000S 0000S               463         .DATA.H DIRDATA, BNKSEC DIRDATA, SIZEOF(DIRDA
                                                   TA)
DC 00000C 0000S 0000S 0000S               464         .DATA.H LIBDATA, BNKSEC LIBDATA, SIZEOF(LIBDA
                                                   TA)
                                          465
DT 000000 ----------<DTRANS>-----------   466         .SECTION  DTRANS,    CONST,  ALIGN=2  ; copy
                                                   table
                                          467         ;    Address         Bank          Address
                                                     Bank          Size
DT 000000 0000S 0000S 0000S 0000S 0000S   468         .DATA.H DCONST,   BNKSEC DCONST,   INIT,   BN
                                                   KSEC INIT,   SIZEOF INIT
DT 00000A 0000S 0000S 0000S 0000S 0000S   469         .DATA.H DIRCONST, BNKSEC DIRCONST, DIRINIT,BN
                                                   KSEC DIRINIT,SIZEOF DIRINIT
DT 000014 0000S 0000S 0000S 0000S 0000S   470