iocc2430.h

Develop Zigbee network real-time Os

/*
 * Copyright (c) 2007 University of Copenhagen
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the
 *   distribution.
 * - Neither the name of University of Copenhagen nor the names of
 *   its contributors may be used to endorse or promote products derived
 *   from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL STANFORD
 * UNIVERSITY OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
 * OF THE POSSIBILITY OF SUCH DAMAGE.
 */
/**
 *
 * Provide cc2430 specific register maps
 *
 * Absolute addressing in Keil is possible in a number of ways:
 *   Standard C
 *     (uint8_t xdata*) addr
 *   Using sfr types/storrage class specifiers
 *     sfr x = addr
 *   Using the at modifier
 *     uint8_t x at addr
 *
 * Regarding multibyte values, it seems that ChipCon has chosen the
 * follwing semantics that handles latching one or more bytes when
 * reading and writing:
 *
 *  When reading: the _low_ byte must be read first and the high-byte
 *  is latched for glitch free 16-bit operations
 *
 *  When writing: the low byte must be written first and the value
 *  does not take effect before the high byte is written
 *
 *
 * @author Martin Leopold <[e-mail]>
 */

#ifndef _H_ioCC2430_H
#define _H_ioCC2430_H

// Get sfr/sbit dummy definitions
# include <io8051.h>

/*
 * Bit locations for IEN0
 */

enum {
  CC2430_IEN0_EA       = 0x7,
  CC2430_IEN0_STIE     = 0x5,
  CC2430_IEN0_ENCIE    = 0x4,
  CC2430_IEN0_URX1IE   = 0x3,
  CC2430_IEN0_URX0IE   = 0x2,
  CC2430_IEN0_ADCIE    = 0x1,
  CC2430_IEN0_RFERRIE  = 0x0
};

/*
 * Bit locations for IEN2
 */

enum {
  CC2430_IEN2_WDTIE  = 0x5,
  CC2430_IEN2_P1IE   = 0x4,
  CC2430_IEN2_UTX1IE = 0x3,
  CC2430_IEN2_UTX0IE = 0x2,
  CC2430_IEN2_P2IE   = 0x1,
  CC2430_IEN2_RFIE   = 0x0
};

/*
 * Bit locations for IRCON
 */

enum {
  CC2430_IRCON_STIF   = 0x7,
  CC2430_IRCON_P0IF   = 0x5,
  CC2430_IRCON_T4IF   = 0x4,
  CC2430_IRCON_T3IF   = 0x3,
  CC2430_IRCON_T2IF   = 0x2,
  CC2430_IRCON_T1IF   = 0x1,
  CC2430_IRCON_DMAIF  = 0x0
};

/*
 * Bit locations for IRCON2
 */

enum {
  CC2430_IRCON2_WDTIF  = 0x4,
  CC2430_IRCON2_P1IF   = 0x3,
  CC2430_IRCON2_UTX1IF = 0x2,
  CC2430_IRCON2_UTX0IF = 0x1,
  CC2430_IRCON2_P2IF   = 0x0
};

/*
 * Bit locations for RFIM
 */

enum {
  CC2430_RFIM_RREG_PD  = 0x7,
  CC2430_RFIM_TXDONE   = 0x6,
  CC2430_RFIM_FIFOP    = 0x5,
  CC2430_RFIM_SFD      = 0x4,
  CC2430_RFIM_CCA      = 0x3,
  CC2430_RFIM_CSP_WT   = 0x2,
  CC2430_RFIM_CSP_STOP = 0x1,
  CC2430_RFIM_CSP_INT  = 0x0
};

/*
 * Bit locations for RFIF
 */

enum {
  CC2430_RFIF_RREG_ON  = 0x7,
  CC2430_RFIF_TXDONE   = 0x6,
  CC2430_RFIF_FIFOP    = 0x5,
  CC2430_RFIF_SFD      = 0x4,
  CC2430_RFIF_CCA      = 0x3,
  CC2430_RFIF_CSP_WT   = 0x2,
  CC2430_RFIF_CSP_STOP = 0x1,
  CC2430_RFIF_CSP_INT  = 0x0
};


// Interrupt definitions

#define  SIG_RFERR   __vector_0   /*  RF TX FIFO Underflow and RX FIFO Overflow   */
#define  SIG_ADC     __vector_1   /*  ADC End of Conversion                       */
#define  SIG_URX0    __vector_2   /*  USART0 RX Complete                          */
#define  SIG_URX1    __vector_3   /*  USART1 RX Complete                          */
#define  SIG_ENC     __vector_4   /*  AES Encryption/Decryption Complete          */
#define  SIG_ST      __vector_5   /*  Sleep Timer Compare                         */
#define  SIG_P2INT   __vector_6   /*  Port 2 Inputs                               */
#define  SIG_UTX0    __vector_7   /*  USART0 TX Complete                          */
#define  SIG_DMA     __vector_8   /*  DMA Transfer Complete                       */
#define  SIG_T1      __vector_9   /*  Timer 1 (16-bit) Capture/Compare/Overflow   */
#define  SIG_T2      __vector_10  /*  Timer 2 (MAC Timer)                         */
#define  SIG_T3      __vector_11  /*  Timer 3 (8-bit) Capture/Compare/Overflow    */
#define  SIG_T4      __vector_12  /*  Timer 4 (8-bit) Capture/Compare/Overflow    */
#define  SIG_P0INT   __vector_13  /*  Port 0 Inputs                               */
#define  SIG_UTX1    __vector_14  /*  USART1 TX Complete                          */
#define  SIG_P1INT   __vector_15  /*  Port 1 Inputs                               */
#define  SIG_RF      __vector_16  /*  RF General Interrupts                       */
#define  SIG_WDT     __vector_17  /*  Watchdog Overflow in Timer Mode             */

uint8_t volatile U0CSR __attribute((sfrAT0x86)); /*  USART 0 Control and Status                      */

//uint8_t volatile TCON      __attribute((sfrAT0x88));
uint8_t volatile P0IFG     __attribute((sfrAT0x89));   /*  Port 0 Interrupt Status Flag         */
uint8_t volatile P1IFG     __attribute((sfrAT0x8A));   /*  Port 1 Interrupt Status Flag         */
uint8_t volatile P2IFG     __attribute((sfrAT0x8B));   /*  Port 2 Interrupt Status Flag         */
uint8_t volatile PICTL     __attribute((sfrAT0x8C));   /*  Port Interrupt Control               */
uint8_t volatile P1IEN     __attribute((sfrAT0x8D));   /*  Port 1 Interrupt Mask                */
uint8_t volatile P0INP     __attribute((sfrAT0x8F));   /*  Port 0 Input Mode                    */

/* TCON sbit definitions */
uint8_t volatile URX1IF    __attribute((sbitAT0x8F));   /*  USART1 RX Interrupt Flag          */
uint8_t volatile _TCON6    __attribute((sbitAT0x8E));   /*  not used                          */
uint8_t volatile ADCIF     __attribute((sbitAT0x8D));   /*  ADC Interrupt Flag                */
uint8_t volatile _TCON5    __attribute((sbitAT0x8C));   /*  not used                          */
uint8_t volatile URX0IF    __attribute((sbitAT0x8B));   /*  USART0 RX Interrupt Flag          */
uint8_t volatile IT1       __attribute((sbitAT0x8A));   /*  reserved (must always be set to 1)*/
uint8_t volatile RFERRIF   __attribute((sbitAT0x89));   /*  RF TX/RX FIFO Interrupt Flag      */
uint8_t volatile IT0       __attribute((sbitAT0x88));   /*  reserved (must always be set to 1)*/

/* Port 1 */
// io8051.h uint8_t volatile  P1        __attribute((sfrAT0x90));
uint8_t volatile  RFIM      __attribute((sfrAT0x91));   /*  RF Interrupt Mask                  */
uint8_t volatile  DPS       __attribute((sfrAT0x92));   /*  Data Pointer Select                */
uint8_t volatile  MPAGE     __attribute((sfrAT0x93));   /*  Memory Page Select                 */
uint8_t volatile  T2CMP     __attribute((sfrAT0x94));   /*  Timer 2 Compare Value              */
uint8_t volatile  ST0       __attribute((sfrAT0x95));   /*  Sleep Timer 0                      */
uint8_t volatile  ST1       __attribute((sfrAT0x96));   /*  Sleep Timer 1                      */
uint8_t volatile  ST2       __attribute((sfrAT0x97));   /*  Sleep Timer 2                      */

/* Interrupt Enable 2 - IEN2 sfr */

uint8_t volatile IEN2       __attribute((sfrAT0x9A));   /*  Interrupt Enable 2           */
uint8_t volatile S1CON      __attribute((sfrAT0x9B));   /*  Interrupt Flags 3            */
uint8_t volatile T2PEROF0   __attribute((sfrAT0x9C));   /*  Timer 2 Overflow Count 0     */
uint8_t volatile T2PEROF1   __attribute((sfrAT0x9D));   /*  Timer 2 Overflow Count 1     */
uint8_t volatile T2PEROF2   __attribute((sfrAT0x9E));   /*  Timer 2 Overflow Count 2     */

uint8_t volatile  T2OF0     __attribute((sfrAT0xA1));   /*  Timer 2 Overflow Count 0     */
uint8_t volatile  T2OF1     __attribute((sfrAT0xA2));   /*  Timer 2 Overflow Count 1     */
uint8_t volatile  T2OF2     __attribute((sfrAT0xA3));   /*  Timer 2 Overflow Count 2     */
uint8_t volatile  T2CAPLPL  __attribute((sfrAT0xA4));   /*  Timer 2 Period Low Byte      */
uint8_t volatile  T2CAPHPH  __attribute((sfrAT0xA5));   /*  Timer 2 Period High Byte     */
uint8_t volatile  T2TLD     __attribute((sfrAT0xA6));   /*  Timer 2 Timer Value Low Byte */
uint8_t volatile  T2THD     __attribute((sfrAT0xA7));   /*  Timer 2 Timer Value High Byte*/

/*  Interrupt Enable 0  */

uint8_t volatile  IEN0    __attribute((sbitAT0xA8)); /* Also known as IE */
uint8_t volatile RFERRIE __attribute((sbitAT0xA8)); /*  RF TX/RX FIFO Interrupt Enable */
uint8_t volatile ADCIE   __attribute((sbitAT0xA9)); /*  ADC Interrupt Enable           */
uint8_t volatile URX0IE  __attribute((sbitAT0xAA)); /*  USART0 RX Interrupt Enable     */
uint8_t volatile URX1IE  __attribute((sbitAT0xAB)); /*  USART1 RX Interrupt Enable     */
uint8_t volatile ENCIE   __attribute((sbitAT0xAC)); /*  AES Interrupt Enable           */
uint8_t volatile STIE    __attribute((sbitAT0xAD)); /*  Sleep Timer Interrupt Enable   */

uint8_t volatile FWT	__attribute((sfrAT0xAB));
uint8_t volatile FADDRL	__attribute((sfrAT0xAC));
uint8_t volatile FADDRH	__attribute((sfrAT0xAD));
uint8_t volatile FCTL	__attribute((sfrAT0xAE));
uint8_t volatile FWDATA	__attribute((sfrAT0xAF));

/*  Interrupt Enable 1  */

uint8_t volatile IEN1    __attribute((sfrAT0xB8)); /* CC2430 specific interrupt mask  */

uint8_t volatile _IEN17 __attribute((sbitAT0xBF));  /*  not used                   */
uint8_t volatile _IEN16 __attribute((sbitAT0xBE));  /*  not used                   */
uint8_t volatile P0IE   __attribute((sbitAT0xBD));  /*  Port 0 Interrupt Enable    */
uint8_t volatile T4IE   __attribute((sbitAT0xBC));  /*  Timer 4 Interrupt Enable   */
uint8_t volatile T3IE   __attribute((sbitAT0xBB));  /*  Timer 3 Interrupt Enable   */
uint8_t volatile T2IE   __attribute((sbitAT0xBA));  /*  Timer 2 Interrupt Enable   */
uint8_t volatile T1IE   __attribute((sbitAT0xB9));  /*  Timer 1 Interrupt Enable   */
uint8_t volatile DMAIE  __attribute((sbitAT0xB8));  /*  DMA Interrupt Enable       */

uint8_t volatile ENCDI   __attribute((sfrAT0xB1)); /*  Encryption Input Data          */
uint8_t volatile ENCDO   __attribute((sfrAT0xB2)); /*  Encryption Output Data         */
uint8_t volatile ENCCS   __attribute((sfrAT0xB3)); /*  Encryption Control and Status  */
uint8_t volatile ADCCON1 __attribute((sfrAT0xB4)); /*  ADC Control 1                  */
uint8_t volatile ADCCON2 __attribute((sfrAT0xB5)); /*  ADC Control 2                  */
uint8_t volatile ADCCON3 __attribute((sfrAT0xB6)); /*  ADC Control 3                  */
uint8_t volatile IEN1    __attribute((sfrAT0xB8)); /*  Defined in io8051.h            */

uint8_t volatile IP1    __attribute((sfrAT0xB9));  /*  Interrupt Priority 1           */
uint8_t volatile ADCL   __attribute((sfrAT0xBA));  /*  ADC Data Low                   */
uint8_t volatile ADCH   __attribute((sfrAT0xBB));  /*  ADC Data High                  */
uint8_t volatile RNDL   __attribute((sfrAT0xBC));  /*  Random Register Low Byte       */
uint8_t volatile RNDH   __attribute((sfrAT0xBD));  /*  Random Register High Byte      */
uint8_t volatile SLEEP  __attribute((sfrAT0xBE));  /*  Sleep Mode Control             */
uint8_t volatile _SFRBF __attribute((sfrAT0xBF));  /*  not used                       */

norace uint8_t volatile U0BUF  __attribute((sfrAT0xC1)); /*  USART 0 Rx/Tx Data Buffer        */
uint8_t volatile U0BAUD __attribute((sfrAT0xC2)); /*  USART 0 Baud Rate Control               */