zxb.fit.qmsg

步进电机的控制程序

{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "50 unused 3.30 34 16 0 " "Info: Number of I/O pins in group: 50 (unused VREF, 3.30 VCCIO, 34 input, 16 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." {  } {  } 0 0 "I/O standards used: %1!s!" 0 0}  } {  } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0}  } {  } 0 0 "Statistics of %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 3 41 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  41 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 48 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 45 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  45 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 48 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0}  } {  } 0 0 "Statistics of %1!s!" 0 0}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.615 ns register register " "Info: Estimated most critical path is register to register delay of 4.615 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns second_pulse_latch:inst\|second_pulse_out\[4\] 1 REG LAB_X4_Y3 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X4_Y3; Fanout = 7; REG Node = 'second_pulse_latch:inst\|second_pulse_out\[4\]'" {  } { { "d:/programs/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/programs/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { second_pulse_latch:inst|second_pulse_out[4] } "NODE_NAME" } } { "zxb.v" "" { Text "E:/TEST/TEXT12/zxb.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.465 ns) + CELL(0.575 ns) 2.040 ns second_pulse_latch:inst\|Add1~369COUT1 2 COMB LAB_X2_Y4 2 " "Info: 2: + IC(1.465 ns) + CELL(0.575 ns) = 2.040 ns; Loc. = LAB_X2_Y4; Fanout = 2; COMB Node = 'second_pulse_latch:inst\|Add1~369COUT1'" {  } { { "d:/programs/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/programs/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.040 ns" { second_pulse_latch:inst|second_pulse_out[4] second_pulse_latch:inst|Add1~369COUT1 } "NODE_NAME" } } { "zxb.v" "" { Text "E:/TEST/TEXT12/zxb.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 2.120 ns second_pulse_latch:inst\|Add1~367COUT1 3 COMB LAB_X2_Y4 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 2.120 ns; Loc. = LAB_X2_Y4; Fanout = 2; COMB Node = 'second_pulse_latch:inst\|Add1~367COUT1'" {  } { { "d:/programs/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/programs/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { second_pulse_latch:inst|Add1~369COUT1 second_pulse_latch:inst|Add1~367COUT1 } "NODE_NAME" } } { "zxb.v" "" { Text "E:/TEST/TEXT12/zxb.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 2.200 ns second_pulse_latch:inst\|Add1~365COUT1 4 COMB LAB_X2_Y4 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 2.200 ns; Loc. = LAB_X2_Y4; Fanout = 2; COMB Node = 'second_pulse_latch:inst\|Add1~365COUT1'" {  } { { "d:/programs/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/programs/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { second_pulse_latch:inst|Add1~367COUT1 second_pulse_latch:inst|Add1~365COUT1 } "NODE_NAME" } } { "zxb.v" "" { Text "E:/TEST/TEXT12/zxb.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 2.808 ns second_pulse_latch:inst\|Add1~362 5 COMB LAB_X2_Y4 1 " "Info: 5: + IC(0.000 ns) + CELL(0.608 ns) = 2.808 ns; Loc. = LAB_X2_Y4; Fanout = 1; COMB Node = 'second_pulse_latch:inst\|Add1~362'" {  } { { "d:/programs/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/programs/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.608 ns" { second_pulse_latch:inst|Add1~365COUT1 second_pulse_latch:inst|Add1~362 } "NODE_NAME" } } { "zxb.v" "" { Text "E:/TEST/TEXT12/zxb.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.069 ns) + CELL(0.738 ns) 4.615 ns second_pulse_latch:inst\|second_pulse_out\[7\] 6 REG LAB_X4_Y3 5 " "Info: 6: + IC(1.069 ns) + CELL(0.738 ns) = 4.615 ns; Loc. = LAB_X4_Y3; Fanout = 5; REG Node = 'second_pulse_latch:inst\|second_pulse_out\[7\]'" {  } { { "d:/programs/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/programs/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.807 ns" { second_pulse_latch:inst|Add1~362 second_pulse_latch:inst|second_pulse_out[7] } "NODE_NAME" } } { "zxb.v" "" { Text "E:/TEST/TEXT12/zxb.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 45.09 % ) " "Info: Total cell delay = 2.081 ns ( 45.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.534 ns ( 54.91 % ) " "Info: Total interconnect delay = 2.534 ns ( 54.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/programs/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/programs/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.615 ns" { second_pulse_latch:inst|second_pulse_out[4] second_pulse_latch:inst|Add1~369COUT1 second_pulse_latch:inst|Add1~367COUT1 second_pulse_latch:inst|Add1~365COUT1 second_pulse_latch:inst|Add1~362 second_pulse_latch:inst|second_pulse_out[7] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}