zxb.map.qmsg

步进电机的控制程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 16 22:55:36 2008 " "Info: Processing started: Sun Mar 16 22:55:36 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off zxb -c zxb " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off zxb -c zxb" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "zxb.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file zxb.v" { { "Info" "ISGN_ENTITY_NAME" "1 second_pulse_latch " "Info: Found entity 1: second_pulse_latch" {  } { { "zxb.v" "" { Text "E:/TEST/TEXT12/zxb.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "zxb.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file zxb.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 zxb " "Info: Found entity 1: zxb" {  } { { "zxb.bdf" "" { Schematic "E:/TEST/TEXT12/zxb.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "zxb " "Info: Elaborating entity \"zxb\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "second_pulse_latch second_pulse_latch:inst " "Info: Elaborating entity \"second_pulse_latch\" for hierarchy \"second_pulse_latch:inst\"" {  } { { "zxb.bdf" "inst" { Schematic "E:/TEST/TEXT12/zxb.bdf" { { 120 424 688 248 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_2116_UNCONVERTED" "second_pulse_out zxb.v(21) " "Warning (10855): Verilog HDL warning at zxb.v(21): initial value for variable second_pulse_out should be constant" {  } { { "zxb.v" "" { Text "E:/TEST/TEXT12/zxb.v" 21 0 0 } }  } 0 10855 "Verilog HDL warning at %2!s!: initial value for variable %1!s! should be constant" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "99 " "Info: Implemented 99 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "35 " "Info: Implemented 35 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "48 " "Info: Implemented 48 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "119 " "Info: Allocated 119 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 16 22:55:37 2008 " "Info: Processing ended: Sun Mar 16 22:55:37 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}