zxb.map.rpt

步进电机的控制程序

; Number of Removed Registers Reported in Synthesis Report           ; 100                ; 100                ;
; Use smart compilation                                              ; Off                ; Off                ;
+--------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                 ;
+----------------------------------+-----------------+------------------------------------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------------+------------------------------+
; zxb.v                            ; yes             ; User Verilog HDL File              ; E:/TEST/TEXT12/zxb.v         ;
; zxb.bdf                          ; yes             ; User Block Diagram/Schematic File  ; E:/TEST/TEXT12/zxb.bdf       ;
+----------------------------------+-----------------+------------------------------------+------------------------------+


+-----------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary               ;
+---------------------------------------------+-------------+
; Resource                                    ; Usage       ;
+---------------------------------------------+-------------+
; Total logic elements                        ; 48          ;
;     -- Combinational with no register       ; 32          ;
;     -- Register only                        ; 0           ;
;     -- Combinational with a register        ; 16          ;
;                                             ;             ;
; Logic element usage by number of LUT inputs ;             ;
;     -- 4 input functions                    ; 16          ;
;     -- 3 input functions                    ; 30          ;
;     -- 2 input functions                    ; 2           ;
;     -- 1 input functions                    ; 0           ;
;     -- 0 input functions                    ; 0           ;
;                                             ;             ;
; Logic elements by mode                      ;             ;
;     -- normal mode                          ; 18          ;
;     -- arithmetic mode                      ; 30          ;
;     -- qfbk mode                            ; 0           ;
;     -- register cascade mode                ; 0           ;
;     -- synchronous clear/load mode          ; 0           ;
;     -- asynchronous clear/load mode         ; 0           ;
;                                             ;             ;
; Total registers                             ; 16          ;
; Total logic cells in carry chains           ; 32          ;
; I/O pins                                    ; 0           ;
; Maximum fan-out node                        ; acele_decre ;
; Maximum fan-out                             ; 16          ;
; Total fan-out                               ; 190         ;
; Average fan-out                             ; 1.92        ;
+---------------------------------------------+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                               ;
+------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------+
; Compilation Hierarchy Node   ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name          ;
+------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------+
; |zxb                         ; 48 (0)      ; 16           ; 0           ; 0    ; 0            ; 32 (0)       ; 0 (0)             ; 16 (0)           ; 32 (0)          ; 0 (0)      ; |zxb                         ;
;    |second_pulse_latch:inst| ; 48 (48)     ; 16           ; 0           ; 0    ; 0            ; 32 (32)      ; 0 (0)             ; 16 (16)          ; 32 (32)         ; 0 (0)      ; |zxb|second_pulse_latch:inst ;
+------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 16    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                  ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                        ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------+
; 5:1                ; 15 bits   ; 45 LEs        ; 30 LEs               ; 15 LEs                 ; Yes        ; |zxb|second_pulse_latch:inst|second_pulse_out[14] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Sun Mar 16 22:55:36 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off zxb -c zxb
Info: Found 1 design units, including 1 entities, in source file zxb.v
    Info: Found entity 1: second_pulse_latch
Info: Found 1 design units, including 1 entities, in source file zxb.bdf
    Info: Found entity 1: zxb
Info: Elaborating entity "zxb" for the top level hierarchy
Info: Elaborating entity "second_pulse_latch" for hierarchy "second_pulse_latch:inst"
Warning (10855): Verilog HDL warning at zxb.v(21): initial value for variable second_pulse_out should be constant
Info: Implemented 99 device resources after synthesis - the final resource count might be different
    Info: Implemented 35 input pins
    Info: Implemented 16 output pins
    Info: Implemented 48 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Allocated 119 megabytes of memory during processing
    Info: Processing ended: Sun Mar 16 22:55:37 2008
    Info: Elapsed time: 00:00:01