📄 isrtramp.lst
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1 .endif
1
34
35 00007d dma3isr:
36 00007d HWI_enter C54_CNOTPRESERVED, 0ffffh
1 00007d CHK_nargs "HWI_enter", IMRDISABLEMASK
1 .if ($symcmp("", "error") = 0)
1 .emsg "HWI_enter IMRDISABLEMASK error"
1 .endif
1
1 ; Note: global interrupts disabled by C54x on entry into ISR
1
1 00007d EEFF frame -1 ; make hole for SWI_F_exec address
1
TMS320C54x COFF Assembler Version 3.50 Sun Apr 02 13:46:35 2000
Copyright (c) 1996-1999 Texas Instruments Incorporated
isrtramp.asm PAGE 9
1 00007e C54_save C54_ST01AB
2 .if (C54_ST01AB & C54_ST0)
2 00007e 4A06 pshm st0
2 .endif
2 .if (C54_ST01AB & C54_ST1)
2 00007f 4A07 pshm st1
2 .endif
2 .if (C54_ST01AB & C54_A)
2 000080 4A08 pshm al
2 000081 4A09 pshm ah
2 000082 4A0A pshm ag
2 .endif
2 .if (C54_ST01AB & C54_B)
2 000083 4A0B pshm bl
2 000084 4A0C pshm bh
2 000085 4A0D pshm bg
2 .endif
2 .if (C54_ST01AB & C54_TTRN)
2 pshm t
2 pshm trn
2 .endif
2 .if (C54_ST01AB & C54_AR0)
2 pshm ar0
2 .endif
2 .if (C54_ST01AB & C54_AR1)
2 pshm ar1
2 .endif
2 .if (C54_ST01AB & C54_AR2)
2 pshm ar2
2 .endif
2 .if (C54_ST01AB & C54_AR3)
2 pshm ar3
2 .endif
2 .if (C54_ST01AB & C54_AR4)
2 pshm ar4
2 .endif
2 .if (C54_ST01AB & C54_AR5)
2 pshm ar5
2 .endif
2 .if (C54_ST01AB & C54_AR6)
2 pshm ar6
2 .endif
2 .if (C54_ST01AB & C54_AR7)
2 pshm ar7
2 .endif
2 .if (C54_ST01AB & C54_BKBLKRPT)
2 pshm bk
2 pshm brc
2 pshm rsa
2 pshm rea
2 .endif
2 .if (C54_ST01AB & C54_PMST)
2 pshm pmst
2 .endif
1
TMS320C54x COFF Assembler Version 3.50 Sun Apr 02 13:46:35 2000
Copyright (c) 1996-1999 Texas Instruments Incorporated
isrtramp.asm PAGE 10
1 ;
1 ; OVM = C16 = FRCT = CMPT = ARP = 0 for C
1 ; C also requires CPL = 1 but we handle that elsewhere
1 ;
1 000086 F6BE rsbx cpl ; (Pipe 3 Ok for ADDM)
1 000087 F6B7 rsbx c16 ; (Pipe 3 Ok for ADDM)
1 000088 F6B9 rsbx ovm ; (Pipe 3 Ok for ADDM)
1 000089 F6B6 rsbx frct ; (Pipe 3 Ok)
1 00008a F4A0 ld #0, arp ; ARP = 0 for CMPT = 0
1 00008b F6B5 rsbx cmpt ; (Pipe 3 Ok)
1
1 00008c 46F8 ld *(GBL_R_sysdp), dp ; dp = GBL_A_SYSPAGE
00008d 0000!
1 00008e 6B00! addm #1, SWI_D_lock ; SWI_D_lock++
00008f 0001
1 000090 4800 ldm imr, a
1 000091 F120 ld #0ffffh, b
000092 FFFF
1 000093 F793 cmpl b ; b = ~b
1 000094 F180 and a, b
1 000095 8900 stlm b, imr
1 000096 F495 nop ; for pipline latency
1 000097 F495 nop
1 000098 F495 nop
1
1 000099 F6BB rsbx intm ; globally enable interrupts
1 ; to allow nested interrupts
1 00009a C54_save C54_CNOTPRESERVED & ~(C54_ST01AB)
2 .if (C54_CNOTPRESERVED & ~(C54_ST01AB) & C54_ST0)
2 pshm st0
2 .endif
2 .if (C54_CNOTPRESERVED & ~(C54_ST01AB) & C54_ST1)
2 pshm st1
2 .endif
2 .if (C54_CNOTPRESERVED & ~(C54_ST01AB) & C54_A)
2 pshm al
2 pshm ah
2 pshm ag
2 .endif
2 .if (C54_CNOTPRESERVED & ~(C54_ST01AB) & C54_B)
2 pshm bl
2 pshm bh
2 pshm bg
2 .endif
2 .if (C54_CNOTPRESERVED & ~(C54_ST01AB) & C54_TTRN)
2 00009a 4A0E pshm t
2 00009b 4A0F pshm trn
2 .endif
2 .if (C54_CNOTPRESERVED & ~(C54_ST01AB) & C54_AR0)
2 00009c 4A10 pshm ar0
2 .endif
2 .if (C54_CNOTPRESERVED & ~(C54_ST01AB) & C54_AR1)
2 pshm ar1
2 .endif
2 .if (C54_CNOTPRESERVED & ~(C54_ST01AB) & C54_AR2)
TMS320C54x COFF Assembler Version 3.50 Sun Apr 02 13:46:35 2000
Copyright (c) 1996-1999 Texas Instruments Incorporated
isrtramp.asm PAGE 11
2 00009d 4A12 pshm ar2
2 .endif
2 .if (C54_CNOTPRESERVED & ~(C54_ST01AB) & C54_AR3)
2 00009e 4A13 pshm ar3
2 .endif
2 .if (C54_CNOTPRESERVED & ~(C54_ST01AB) & C54_AR4)
2 00009f 4A14 pshm ar4
2 .endif
2 .if (C54_CNOTPRESERVED & ~(C54_ST01AB) & C54_AR5)
2 0000a0 4A15 pshm ar5
2 .endif
2 .if (C54_CNOTPRESERVED & ~(C54_ST01AB) & C54_AR6)
2 pshm ar6
2 .endif
2 .if (C54_CNOTPRESERVED & ~(C54_ST01AB) & C54_AR7)
2 pshm ar7
2 .endif
2 .if (C54_CNOTPRESERVED & ~(C54_ST01AB) & C54_BKBLKRPT)
2 0000a1 4A19 pshm bk
2 0000a2 4A1A pshm brc
2 0000a3 4A1B pshm rsa
2 0000a4 4A1C pshm rea
2 .endif
2 .if (C54_CNOTPRESERVED & ~(C54_ST01AB) & C54_PMST)
2 0000a5 4A1D pshm pmst
2 .endif
1
1 0000a6 4A08 pshm al ; save old imr
1
1 0000a7 4818 ldm sp, a ; let a = sp so we can save it later
1 0000a8 68F8 andm #-2, *(sp) ; let sp contain the lower even address
0000a9 0018
0000aa FFFE
1 0000ab F495 nop ; needed for pipeline latency
1 0000ac F495 nop ; needed for pipeline latency
1 0000ad 4A08 pshm al ; save al which has the sp value to be restored
1
1 ; at this point the sp is odd because of
1 ; the "pshm al" instruction above
1
1 0000ae 4A08 pshm al ; do this so the sp will contain even address
1
1 ; at this point the sp is even because of
1 ; the "pshm al" instruction above
1
1
37 ; cpl = 0
38 ; dp = GBL_A_SYSPAGE
39
40 ; We need to set cpl bit when going to C
41 0000af F7BE ssbx cpl
42 0000b0 F495 nop ; cpl latency
43 0000b1 F495 nop ; cpl latency
44 0000b2 F495 nop ; cpl latency
45
TMS320C54x COFF Assembler Version 3.50 Sun Apr 02 13:46:35 2000
Copyright (c) 1996-1999 Texas Instruments Incorporated
isrtramp.asm PAGE 12
46 0000b3 F074 call _firTxPrime
0000b4 0000!
47
48 0000b5 F6BE rsbx cpl ; HWI_exit precondition
49 0000b6 F495 nop ; cpl latency
50 0000b7 F495 nop ; cpl latency
51 0000b8 F495 nop ; cpl latency
52
53 0000b9 EA00! ld #GBL_A_SYSPAGE, dp
54
55 0000ba HWI_exit C54_CNOTPRESERVED, 0ffffh
1 0000ba CHK_nargs "HWI_exit", IMRRESTOREMASK
1 .if ($symcmp("", "error") = 0)
1 .emsg "HWI_enter IMRRESTOREMASK error"
1 .endif
1
1 0000ba 8A18 popm sp ; restore the sp back to what it was
1 0000bb F495 nop ; needed for pipeline latency
1 0000bc F495 nop ; needed for pipeline latency
1
1 0000bd 8A08 popm al ; get old imr
1
1 0000be C54_restore C54_CNOTPRESERVED & ~(C54_ST01AB)
2 .if (C54_CNOTPRESERVED & ~(C54_ST01AB) & C54_PMST)
2 0000be 8A1D popm pmst
2 .endif
2 .if (C54_CNOTPRESERVED & ~(C54_ST01AB) & C54_BKBLKRPT)
2 0000bf 8A1C popm rea
2 0000c0 8A1B popm rsa
2 0000c1 8A1A popm brc
2 0000c2 8A19 popm bk
2 .endif
2 .if (C54_CNOTPRESERVED & ~(C54_ST01AB) & C54_AR7)
2 popm ar7
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