📄 isrtramp.lst
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TMS320C54x COFF Assembler Version 3.50 Sun Apr 02 13:46:35 2000
Copyright (c) 1996-1999 Texas Instruments Incorporated
isrtramp.asm PAGE 1
1 ;;; Bounce DMA2 and DMA3 isr's to their C implementations after saving
2 ;;; DSP/BIOS state
3
4 ;; DSP/BIOS includes
5 .include c54.h54
6 .include gbl.h54
7 .include hwi.h54
8
9 .ref _firTxPrime, _firRxPrime
10
11 .global dma2isr, dma3isr
12
13 000000 dma2isr:
14 000000 HWI_enter C54_CNOTPRESERVED, 0ffffh
1 000000 CHK_nargs "HWI_enter", IMRDISABLEMASK
1 .if ($symcmp("", "error") = 0)
1 .emsg "HWI_enter IMRDISABLEMASK error"
1 .endif
1
1 ; Note: global interrupts disabled by C54x on entry into ISR
1
1 000000 EEFF frame -1 ; make hole for SWI_F_exec address
1
1 000001 C54_save C54_ST01AB
2 .if (C54_ST01AB & C54_ST0)
2 000001 4A06 pshm st0
2 .endif
2 .if (C54_ST01AB & C54_ST1)
2 000002 4A07 pshm st1
2 .endif
2 .if (C54_ST01AB & C54_A)
2 000003 4A08 pshm al
2 000004 4A09 pshm ah
2 000005 4A0A pshm ag
2 .endif
2 .if (C54_ST01AB & C54_B)
2 000006 4A0B pshm bl
2 000007 4A0C pshm bh
2 000008 4A0D pshm bg
2 .endif
2 .if (C54_ST01AB & C54_TTRN)
2 pshm t
2 pshm trn
2 .endif
2 .if (C54_ST01AB & C54_AR0)
2 pshm ar0
2 .endif
2 .if (C54_ST01AB & C54_AR1)
2 pshm ar1
2 .endif
2 .if (C54_ST01AB & C54_AR2)
2 pshm ar2
2 .endif
2 .if (C54_ST01AB & C54_AR3)
2 pshm ar3
TMS320C54x COFF Assembler Version 3.50 Sun Apr 02 13:46:35 2000
Copyright (c) 1996-1999 Texas Instruments Incorporated
isrtramp.asm PAGE 2
2 .endif
2 .if (C54_ST01AB & C54_AR4)
2 pshm ar4
2 .endif
2 .if (C54_ST01AB & C54_AR5)
2 pshm ar5
2 .endif
2 .if (C54_ST01AB & C54_AR6)
2 pshm ar6
2 .endif
2 .if (C54_ST01AB & C54_AR7)
2 pshm ar7
2 .endif
2 .if (C54_ST01AB & C54_BKBLKRPT)
2 pshm bk
2 pshm brc
2 pshm rsa
2 pshm rea
2 .endif
2 .if (C54_ST01AB & C54_PMST)
2 pshm pmst
2 .endif
1
1 ;
1 ; OVM = C16 = FRCT = CMPT = ARP = 0 for C
1 ; C also requires CPL = 1 but we handle that elsewhere
1 ;
1 000009 F6BE rsbx cpl ; (Pipe 3 Ok for ADDM)
1 00000a F6B7 rsbx c16 ; (Pipe 3 Ok for ADDM)
1 00000b F6B9 rsbx ovm ; (Pipe 3 Ok for ADDM)
1 00000c F6B6 rsbx frct ; (Pipe 3 Ok)
1 00000d F4A0 ld #0, arp ; ARP = 0 for CMPT = 0
1 00000e F6B5 rsbx cmpt ; (Pipe 3 Ok)
1
1 00000f 46F8 ld *(GBL_R_sysdp), dp ; dp = GBL_A_SYSPAGE
000010 0000!
1 000011 6B00! addm #1, SWI_D_lock ; SWI_D_lock++
000012 0001
1 000013 4800 ldm imr, a
1 000014 F120 ld #0ffffh, b
000015 FFFF
1 000016 F793 cmpl b ; b = ~b
1 000017 F180 and a, b
1 000018 8900 stlm b, imr
1 000019 F495 nop ; for pipline latency
1 00001a F495 nop
1 00001b F495 nop
1
1 00001c F6BB rsbx intm ; globally enable interrupts
1 ; to allow nested interrupts
1 00001d C54_save C54_CNOTPRESERVED & ~(C54_ST01AB)
2 .if (C54_CNOTPRESERVED & ~(C54_ST01AB) & C54_ST0)
2 pshm st0
2 .endif
2 .if (C54_CNOTPRESERVED & ~(C54_ST01AB) & C54_ST1)
TMS320C54x COFF Assembler Version 3.50 Sun Apr 02 13:46:35 2000
Copyright (c) 1996-1999 Texas Instruments Incorporated
isrtramp.asm PAGE 3
2 pshm st1
2 .endif
2 .if (C54_CNOTPRESERVED & ~(C54_ST01AB) & C54_A)
2 pshm al
2 pshm ah
2 pshm ag
2 .endif
2 .if (C54_CNOTPRESERVED & ~(C54_ST01AB) & C54_B)
2 pshm bl
2 pshm bh
2 pshm bg
2 .endif
2 .if (C54_CNOTPRESERVED & ~(C54_ST01AB) & C54_TTRN)
2 00001d 4A0E pshm t
2 00001e 4A0F pshm trn
2 .endif
2 .if (C54_CNOTPRESERVED & ~(C54_ST01AB) & C54_AR0)
2 00001f 4A10 pshm ar0
2 .endif
2 .if (C54_CNOTPRESERVED & ~(C54_ST01AB) & C54_AR1)
2 pshm ar1
2 .endif
2 .if (C54_CNOTPRESERVED & ~(C54_ST01AB) & C54_AR2)
2 000020 4A12 pshm ar2
2 .endif
2 .if (C54_CNOTPRESERVED & ~(C54_ST01AB) & C54_AR3)
2 000021 4A13 pshm ar3
2 .endif
2 .if (C54_CNOTPRESERVED & ~(C54_ST01AB) & C54_AR4)
2 000022 4A14 pshm ar4
2 .endif
2 .if (C54_CNOTPRESERVED & ~(C54_ST01AB) & C54_AR5)
2 000023 4A15 pshm ar5
2 .endif
2 .if (C54_CNOTPRESERVED & ~(C54_ST01AB) & C54_AR6)
2 pshm ar6
2 .endif
2 .if (C54_CNOTPRESERVED & ~(C54_ST01AB) & C54_AR7)
2 pshm ar7
2 .endif
2 .if (C54_CNOTPRESERVED & ~(C54_ST01AB) & C54_BKBLKRPT)
2 000024 4A19 pshm bk
2 000025 4A1A pshm brc
2 000026 4A1B pshm rsa
2 000027 4A1C pshm rea
2 .endif
2 .if (C54_CNOTPRESERVED & ~(C54_ST01AB) & C54_PMST)
2 000028 4A1D pshm pmst
2 .endif
1
1 000029 4A08 pshm al ; save old imr
1
1 00002a 4818 ldm sp, a ; let a = sp so we can save it later
1 00002b 68F8 andm #-2, *(sp) ; let sp contain the lower even address
00002c 0018
TMS320C54x COFF Assembler Version 3.50 Sun Apr 02 13:46:35 2000
Copyright (c) 1996-1999 Texas Instruments Incorporated
isrtramp.asm PAGE 4
00002d FFFE
1 00002e F495 nop ; needed for pipeline latency
1 00002f F495 nop ; needed for pipeline latency
1 000030 4A08 pshm al ; save al which has the sp value to be restored
1
1 ; at this point the sp is odd because of
1 ; the "pshm al" instruction above
1
1 000031 4A08 pshm al ; do this so the sp will contain even address
1
1 ; at this point the sp is even because of
1 ; the "pshm al" instruction above
1
1
15 ; cpl = 0
16 ; dp = GBL_A_SYSPAGE
17
18 ; We need to set cpl bit when going to C
19 000032 F7BE ssbx cpl
20 000033 F495 nop ; cpl latency
21 000034 F495 nop ; cpl latency
22 000035 F495 nop ; cpl latency
23
24 000036 F074 call _firRxPrime
000037 0000!
25
26 000038 F6BE rsbx cpl ; HWI_exit precondition
27 000039 F495 nop ; cpl latency
28 00003a F495 nop ; cpl latency
29 00003b F495 nop ; cpl latency
30
31 00003c EA00! ld #GBL_A_SYSPAGE, dp
32
33 00003d HWI_exit C54_CNOTPRESERVED, 0ffffh
1 00003d CHK_nargs "HWI_exit", IMRRESTOREMASK
1 .if ($symcmp("", "error") = 0)
1 .emsg "HWI_enter IMRRESTOREMASK error"
1 .endif
1
1 00003d 8A18 popm sp ; restore the sp back to what it was
1 00003e F495 nop ; needed for pipeline latency
1 00003f F495 nop ; needed for pipeline latency
1
1 000040 8A08 popm al ; get old imr
1
1 000041 C54_restore C54_CNOTPRESERVED & ~(C54_ST01AB)
2 .if (C54_CNOTPRESERVED & ~(C54_ST01AB) & C54_PMST)
2 000041 8A1D popm pmst
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