📄 psocgpioint.h
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BYTE CSD_1SW0_IntEn_ADDR;
#define CSD_1SW0_MASK 0x4
#pragma ioport CSD_1SW0_MUXBusCtrl_ADDR: 0x1ec
BYTE CSD_1SW0_MUXBusCtrl_ADDR;
// CSD_1SW0 Shadow defines
// CSD_1SW0_DataShadow define
extern BYTE Port_4_Data_SHADE;
#define CSD_1SW0_DataShadow (*(unsigned char*)&Port_4_Data_SHADE)
// CSD_1SW18 address and mask defines
#pragma ioport CSD_1SW18_Data_ADDR: 0x10
BYTE CSD_1SW18_Data_ADDR;
#pragma ioport CSD_1SW18_DriveMode_0_ADDR: 0x110
BYTE CSD_1SW18_DriveMode_0_ADDR;
#pragma ioport CSD_1SW18_DriveMode_1_ADDR: 0x111
BYTE CSD_1SW18_DriveMode_1_ADDR;
#pragma ioport CSD_1SW18_DriveMode_2_ADDR: 0x13
BYTE CSD_1SW18_DriveMode_2_ADDR;
#pragma ioport CSD_1SW18_GlobalSelect_ADDR: 0x12
BYTE CSD_1SW18_GlobalSelect_ADDR;
#pragma ioport CSD_1SW18_IntCtrl_0_ADDR: 0x112
BYTE CSD_1SW18_IntCtrl_0_ADDR;
#pragma ioport CSD_1SW18_IntCtrl_1_ADDR: 0x113
BYTE CSD_1SW18_IntCtrl_1_ADDR;
#pragma ioport CSD_1SW18_IntEn_ADDR: 0x11
BYTE CSD_1SW18_IntEn_ADDR;
#define CSD_1SW18_MASK 0x8
#pragma ioport CSD_1SW18_MUXBusCtrl_ADDR: 0x1ec
BYTE CSD_1SW18_MUXBusCtrl_ADDR;
// CSD_1SW18 Shadow defines
// CSD_1SW18_DataShadow define
extern BYTE Port_4_Data_SHADE;
#define CSD_1SW18_DataShadow (*(unsigned char*)&Port_4_Data_SHADE)
// CSD_1SW8 address and mask defines
#pragma ioport CSD_1SW8_Data_ADDR: 0x10
BYTE CSD_1SW8_Data_ADDR;
#pragma ioport CSD_1SW8_DriveMode_0_ADDR: 0x110
BYTE CSD_1SW8_DriveMode_0_ADDR;
#pragma ioport CSD_1SW8_DriveMode_1_ADDR: 0x111
BYTE CSD_1SW8_DriveMode_1_ADDR;
#pragma ioport CSD_1SW8_DriveMode_2_ADDR: 0x13
BYTE CSD_1SW8_DriveMode_2_ADDR;
#pragma ioport CSD_1SW8_GlobalSelect_ADDR: 0x12
BYTE CSD_1SW8_GlobalSelect_ADDR;
#pragma ioport CSD_1SW8_IntCtrl_0_ADDR: 0x112
BYTE CSD_1SW8_IntCtrl_0_ADDR;
#pragma ioport CSD_1SW8_IntCtrl_1_ADDR: 0x113
BYTE CSD_1SW8_IntCtrl_1_ADDR;
#pragma ioport CSD_1SW8_IntEn_ADDR: 0x11
BYTE CSD_1SW8_IntEn_ADDR;
#define CSD_1SW8_MASK 0x10
#pragma ioport CSD_1SW8_MUXBusCtrl_ADDR: 0x1ec
BYTE CSD_1SW8_MUXBusCtrl_ADDR;
// CSD_1SW8 Shadow defines
// CSD_1SW8_DataShadow define
extern BYTE Port_4_Data_SHADE;
#define CSD_1SW8_DataShadow (*(unsigned char*)&Port_4_Data_SHADE)
// CSD_1SW26 address and mask defines
#pragma ioport CSD_1SW26_Data_ADDR: 0x10
BYTE CSD_1SW26_Data_ADDR;
#pragma ioport CSD_1SW26_DriveMode_0_ADDR: 0x110
BYTE CSD_1SW26_DriveMode_0_ADDR;
#pragma ioport CSD_1SW26_DriveMode_1_ADDR: 0x111
BYTE CSD_1SW26_DriveMode_1_ADDR;
#pragma ioport CSD_1SW26_DriveMode_2_ADDR: 0x13
BYTE CSD_1SW26_DriveMode_2_ADDR;
#pragma ioport CSD_1SW26_GlobalSelect_ADDR: 0x12
BYTE CSD_1SW26_GlobalSelect_ADDR;
#pragma ioport CSD_1SW26_IntCtrl_0_ADDR: 0x112
BYTE CSD_1SW26_IntCtrl_0_ADDR;
#pragma ioport CSD_1SW26_IntCtrl_1_ADDR: 0x113
BYTE CSD_1SW26_IntCtrl_1_ADDR;
#pragma ioport CSD_1SW26_IntEn_ADDR: 0x11
BYTE CSD_1SW26_IntEn_ADDR;
#define CSD_1SW26_MASK 0x20
#pragma ioport CSD_1SW26_MUXBusCtrl_ADDR: 0x1ec
BYTE CSD_1SW26_MUXBusCtrl_ADDR;
// CSD_1SW26 Shadow defines
// CSD_1SW26_DataShadow define
extern BYTE Port_4_Data_SHADE;
#define CSD_1SW26_DataShadow (*(unsigned char*)&Port_4_Data_SHADE)
// CSD_1SW15 address and mask defines
#pragma ioport CSD_1SW15_Data_ADDR: 0x10
BYTE CSD_1SW15_Data_ADDR;
#pragma ioport CSD_1SW15_DriveMode_0_ADDR: 0x110
BYTE CSD_1SW15_DriveMode_0_ADDR;
#pragma ioport CSD_1SW15_DriveMode_1_ADDR: 0x111
BYTE CSD_1SW15_DriveMode_1_ADDR;
#pragma ioport CSD_1SW15_DriveMode_2_ADDR: 0x13
BYTE CSD_1SW15_DriveMode_2_ADDR;
#pragma ioport CSD_1SW15_GlobalSelect_ADDR: 0x12
BYTE CSD_1SW15_GlobalSelect_ADDR;
#pragma ioport CSD_1SW15_IntCtrl_0_ADDR: 0x112
BYTE CSD_1SW15_IntCtrl_0_ADDR;
#pragma ioport CSD_1SW15_IntCtrl_1_ADDR: 0x113
BYTE CSD_1SW15_IntCtrl_1_ADDR;
#pragma ioport CSD_1SW15_IntEn_ADDR: 0x11
BYTE CSD_1SW15_IntEn_ADDR;
#define CSD_1SW15_MASK 0x40
#pragma ioport CSD_1SW15_MUXBusCtrl_ADDR: 0x1ec
BYTE CSD_1SW15_MUXBusCtrl_ADDR;
// CSD_1SW15 Shadow defines
// CSD_1SW15_DataShadow define
extern BYTE Port_4_Data_SHADE;
#define CSD_1SW15_DataShadow (*(unsigned char*)&Port_4_Data_SHADE)
// CSD_1SW33 address and mask defines
#pragma ioport CSD_1SW33_Data_ADDR: 0x10
BYTE CSD_1SW33_Data_ADDR;
#pragma ioport CSD_1SW33_DriveMode_0_ADDR: 0x110
BYTE CSD_1SW33_DriveMode_0_ADDR;
#pragma ioport CSD_1SW33_DriveMode_1_ADDR: 0x111
BYTE CSD_1SW33_DriveMode_1_ADDR;
#pragma ioport CSD_1SW33_DriveMode_2_ADDR: 0x13
BYTE CSD_1SW33_DriveMode_2_ADDR;
#pragma ioport CSD_1SW33_GlobalSelect_ADDR: 0x12
BYTE CSD_1SW33_GlobalSelect_ADDR;
#pragma ioport CSD_1SW33_IntCtrl_0_ADDR: 0x112
BYTE CSD_1SW33_IntCtrl_0_ADDR;
#pragma ioport CSD_1SW33_IntCtrl_1_ADDR: 0x113
BYTE CSD_1SW33_IntCtrl_1_ADDR;
#pragma ioport CSD_1SW33_IntEn_ADDR: 0x11
BYTE CSD_1SW33_IntEn_ADDR;
#define CSD_1SW33_MASK 0x80
#pragma ioport CSD_1SW33_MUXBusCtrl_ADDR: 0x1ec
BYTE CSD_1SW33_MUXBusCtrl_ADDR;
// CSD_1SW33 Shadow defines
// CSD_1SW33_DataShadow define
extern BYTE Port_4_Data_SHADE;
#define CSD_1SW33_DataShadow (*(unsigned char*)&Port_4_Data_SHADE)
// CSD_1SW5 address and mask defines
#pragma ioport CSD_1SW5_Data_ADDR: 0x14
BYTE CSD_1SW5_Data_ADDR;
#pragma ioport CSD_1SW5_DriveMode_0_ADDR: 0x114
BYTE CSD_1SW5_DriveMode_0_ADDR;
#pragma ioport CSD_1SW5_DriveMode_1_ADDR: 0x115
BYTE CSD_1SW5_DriveMode_1_ADDR;
#pragma ioport CSD_1SW5_DriveMode_2_ADDR: 0x17
BYTE CSD_1SW5_DriveMode_2_ADDR;
#pragma ioport CSD_1SW5_GlobalSelect_ADDR: 0x16
BYTE CSD_1SW5_GlobalSelect_ADDR;
#pragma ioport CSD_1SW5_IntCtrl_0_ADDR: 0x116
BYTE CSD_1SW5_IntCtrl_0_ADDR;
#pragma ioport CSD_1SW5_IntCtrl_1_ADDR: 0x117
BYTE CSD_1SW5_IntCtrl_1_ADDR;
#pragma ioport CSD_1SW5_IntEn_ADDR: 0x15
BYTE CSD_1SW5_IntEn_ADDR;
#define CSD_1SW5_MASK 0x1
#pragma ioport CSD_1SW5_MUXBusCtrl_ADDR: 0x1ed
BYTE CSD_1SW5_MUXBusCtrl_ADDR;
// CSD_1SW5 Shadow defines
// CSD_1SW5_DataShadow define
extern BYTE Port_5_Data_SHADE;
#define CSD_1SW5_DataShadow (*(unsigned char*)&Port_5_Data_SHADE)
// CSD_1SW19 address and mask defines
#pragma ioport CSD_1SW19_Data_ADDR: 0x14
BYTE CSD_1SW19_Data_ADDR;
#pragma ioport CSD_1SW19_DriveMode_0_ADDR: 0x114
BYTE CSD_1SW19_DriveMode_0_ADDR;
#pragma ioport CSD_1SW19_DriveMode_1_ADDR: 0x115
BYTE CSD_1SW19_DriveMode_1_ADDR;
#pragma ioport CSD_1SW19_DriveMode_2_ADDR: 0x17
BYTE CSD_1SW19_DriveMode_2_ADDR;
#pragma ioport CSD_1SW19_GlobalSelect_ADDR: 0x16
BYTE CSD_1SW19_GlobalSelect_ADDR;
#pragma ioport CSD_1SW19_IntCtrl_0_ADDR: 0x116
BYTE CSD_1SW19_IntCtrl_0_ADDR;
#pragma ioport CSD_1SW19_IntCtrl_1_ADDR: 0x117
BYTE CSD_1SW19_IntCtrl_1_ADDR;
#pragma ioport CSD_1SW19_IntEn_ADDR: 0x15
BYTE CSD_1SW19_IntEn_ADDR;
#define CSD_1SW19_MASK 0x2
#pragma ioport CSD_1SW19_MUXBusCtrl_ADDR: 0x1ed
BYTE CSD_1SW19_MUXBusCtrl_ADDR;
// CSD_1SW19 Shadow defines
// CSD_1SW19_DataShadow define
extern BYTE Port_5_Data_SHADE;
#define CSD_1SW19_DataShadow (*(unsigned char*)&Port_5_Data_SHADE)
// CSD_1SW11 address and mask defines
#pragma ioport CSD_1SW11_Data_ADDR: 0x14
BYTE CSD_1SW11_Data_ADDR;
#pragma ioport CSD_1SW11_DriveMode_0_ADDR: 0x114
BYTE CSD_1SW11_DriveMode_0_ADDR;
#pragma ioport CSD_1SW11_DriveMode_1_ADDR: 0x115
BYTE CSD_1SW11_DriveMode_1_ADDR;
#pragma ioport CSD_1SW11_DriveMode_2_ADDR: 0x17
BYTE CSD_1SW11_DriveMode_2_ADDR;
#pragma ioport CSD_1SW11_GlobalSelect_ADDR: 0x16
BYTE CSD_1SW11_GlobalSelect_ADDR;
#pragma ioport CSD_1SW11_IntCtrl_0_ADDR: 0x116
BYTE CSD_1SW11_IntCtrl_0_ADDR;
#pragma ioport CSD_1SW11_IntCtrl_1_ADDR: 0x117
BYTE CSD_1SW11_IntCtrl_1_ADDR;
#pragma ioport CSD_1SW11_IntEn_ADDR: 0x15
BYTE CSD_1SW11_IntEn_ADDR;
#define CSD_1SW11_MASK 0x4
#pragma ioport CSD_1SW11_MUXBusCtrl_ADDR: 0x1ed
BYTE CSD_1SW11_MUXBusCtrl_ADDR;
// CSD_1SW11 Shadow defines
// CSD_1SW11_DataShadow define
extern BYTE Port_5_Data_SHADE;
#define CSD_1SW11_DataShadow (*(unsigned char*)&Port_5_Data_SHADE)
// CSD_1SW23 address and mask defines
#pragma ioport CSD_1SW23_Data_ADDR: 0x14
BYTE CSD_1SW23_Data_ADDR;
#pragma ioport CSD_1SW23_DriveMode_0_ADDR: 0x114
BYTE CSD_1SW23_DriveMode_0_ADDR;
#pragma ioport CSD_1SW23_DriveMode_1_ADDR: 0x115
BYTE CSD_1SW23_DriveMode_1_ADDR;
#pragma ioport CSD_1SW23_DriveMode_2_ADDR: 0x17
BYTE CSD_1SW23_DriveMode_2_ADDR;
#pragma ioport CSD_1SW23_GlobalSelect_ADDR: 0x16
BYTE CSD_1SW23_GlobalSelect_ADDR;
#pragma ioport CSD_1SW23_IntCtrl_0_ADDR: 0x116
BYTE CSD_1SW23_IntCtrl_0_ADDR;
#pragma ioport CSD_1SW23_IntCtrl_1_ADDR: 0x117
BYTE CSD_1SW23_IntCtrl_1_ADDR;
#pragma ioport CSD_1SW23_IntEn_ADDR: 0x15
BYTE CSD_1SW23_IntEn_ADDR;
#define CSD_1SW23_MASK 0x8
#pragma ioport CSD_1SW23_MUXBusCtrl_ADDR: 0x1ed
BYTE CSD_1SW23_MUXBusCtrl_ADDR;
// CSD_1SW23 Shadow defines
// CSD_1SW23_DataShadow define
extern BYTE Port_5_Data_SHADE;
#define CSD_1SW23_DataShadow (*(unsigned char*)&Port_5_Data_SHADE)
// CSD_1SW1 address and mask defines
#pragma ioport CSD_1SW1_Data_ADDR: 0x14
BYTE CSD_1SW1_Data_ADDR;
#pragma ioport CSD_1SW1_DriveMode_0_ADDR: 0x114
BYTE CSD_1SW1_DriveMode_0_ADDR;
#pragma ioport CSD_1SW1_DriveMode_1_ADDR: 0x115
BYTE CSD_1SW1_DriveMode_1_ADDR;
#pragma ioport CSD_1SW1_DriveMode_2_ADDR: 0x17
BYTE CSD_1SW1_DriveMode_2_ADDR;
#pragma ioport CSD_1SW1_GlobalSelect_ADDR: 0x16
BYTE CSD_1SW1_GlobalSelect_ADDR;
#pragma ioport CSD_1SW1_IntCtrl_0_ADDR: 0x116
BYTE CSD_1SW1_IntCtrl_0_ADDR;
#pragma ioport CSD_1SW1_IntCtrl_1_ADDR: 0x117
BYTE CSD_1SW1_IntCtrl_1_ADDR;
#pragma ioport CSD_1SW1_IntEn_ADDR: 0x15
BYTE CSD_1SW1_IntEn_ADDR;
#define CSD_1SW1_MASK 0x10
#pragma ioport CSD_1SW1_MUXBusCtrl_ADDR: 0x1ed
BYTE CSD_1SW1_MUXBusCtrl_ADDR;
// CSD_1SW1 Shadow defines
// CSD_1SW1_DataShadow define
extern BYTE Port_5_Data_SHADE;
#define CSD_1SW1_DataShadow (*(unsigned char*)&Port_5_Data_SHADE)
// CSD_1SW29 address and mask defines
#pragma ioport CSD_1SW29_Data_ADDR: 0x14
BYTE CSD_1SW29_Data_ADDR;
#pragma ioport CSD_1SW29_DriveMode_0_ADDR: 0x114
BYTE CSD_1SW29_DriveMode_0_ADDR;
#pragma ioport CSD_1SW29_DriveMode_1_ADDR: 0x115
BYTE CSD_1SW29_DriveMode_1_ADDR;
#pragma ioport CSD_1SW29_DriveMode_2_ADDR: 0x17
BYTE CSD_1SW29_DriveMode_2_ADDR;
#pragma ioport CSD_1SW29_GlobalSelect_ADDR: 0x16
BYTE CSD_1SW29_GlobalSelect_ADDR;
#pragma ioport CSD_1SW29_IntCtrl_0_ADDR: 0x116
BYTE CSD_1SW29_IntCtrl_0_ADDR;
#pragma ioport CSD_1SW29_IntCtrl_1_ADDR: 0x117
BYTE CSD_1SW29_IntCtrl_1_ADDR;
#pragma ioport CSD_1SW29_IntEn_ADDR: 0x15
BYTE CSD_1SW29_IntEn_ADDR;
#define CSD_1SW29_MASK 0x20
#pragma ioport CSD_1SW29_MUXBusCtrl_ADDR: 0x1ed
BYTE CSD_1SW29_MUXBusCtrl_ADDR;
// CSD_1SW29 Shadow defines
// CSD_1SW29_DataShadow define
extern BYTE Port_5_Data_SHADE;
#define CSD_1SW29_DataShadow (*(unsigned char*)&Port_5_Data_SHADE)
// CSD_1SW12 address and mask defines
#pragma ioport CSD_1SW12_Data_ADDR: 0x14
BYTE CSD_1SW12_Data_ADDR;
#pragma ioport CSD_1SW12_DriveMode_0_ADDR: 0x114
BYTE CSD_1SW12_DriveMode_0_ADDR;
#pragma ioport CSD_1SW12_DriveMode_1_ADDR: 0x115
BYTE CSD_1SW12_DriveMode_1_ADDR;
#pragma ioport CSD_1SW12_DriveMode_2_ADDR: 0x17
BYTE CSD_1SW12_DriveMode_2_ADDR;
#pragma ioport CSD_1SW12_GlobalSelect_ADDR: 0x16
BYTE CSD_1SW12_GlobalSelect_ADDR;
#pragma ioport CSD_1SW12_IntCtrl_0_ADDR: 0x116
BYTE CSD_1SW12_IntCtrl_0_ADDR;
#pragma ioport CSD_1SW12_IntCtrl_1_ADDR: 0x117
BYTE CSD_1SW12_IntCtrl_1_ADDR;
#pragma ioport CSD_1SW12_IntEn_ADDR: 0x15
BYTE CSD_1SW12_IntEn_ADDR;
#define CSD_1SW12_MASK 0x40
#pragma ioport CSD_1SW12_MUXBusCtrl_ADDR: 0x1ed
BYTE CSD_1SW12_MUXBusCtrl_ADDR;
// CSD_1SW12 Shadow defines
// CSD_1SW12_DataShadow define
extern BYTE Port_5_Data_SHADE;
#define CSD_1SW12_DataShadow (*(unsigned char*)&Port_5_Data_SHADE)
// CSD_1SW30 address and mask defines
#pragma ioport CSD_1SW30_Data_ADDR: 0x14
BYTE CSD_1SW30_Data_ADDR;
#pragma ioport CSD_1SW30_DriveMode_0_ADDR: 0x114
BYTE CSD_1SW30_DriveMode_0_ADDR;
#pragma ioport CSD_1SW30_DriveMode_1_ADDR: 0x115
BYTE CSD_1SW30_DriveMode_1_ADDR;
#pragma ioport CSD_1SW30_DriveMode_2_ADDR: 0x17
BYTE CSD_1SW30_DriveMode_2_ADDR;
#pragma ioport CSD_1SW30_GlobalSelect_ADDR: 0x16
BYTE CSD_1SW30_GlobalSelect_ADDR;
#pragma ioport CSD_1SW30_IntCtrl_0_ADDR: 0x116
BYTE CSD_1SW30_IntCtrl_0_ADDR;
#pragma ioport CSD_1SW30_IntCtrl_1_ADDR: 0x117
BYTE CSD_1SW30_IntCtrl_1_ADDR;
#pragma ioport CSD_1SW30_IntEn_ADDR: 0x15
BYTE CSD_1SW30_IntEn_ADDR;
#define CSD_1SW30_MASK 0x80
#pragma ioport CSD_1SW30_MUXBusCtrl_ADDR: 0x1ed
BYTE CSD_1SW30_MUXBusCtrl_ADDR;
// CSD_1SW30 Shadow defines
// CSD_1SW30_DataShadow define
extern BYTE Port_5_Data_SHADE;
#define CSD_1SW30_DataShadow (*(unsigned char*)&Port_5_Data_SHADE)
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