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📄 psocgpioint.h

📁 cypresscy74294ic键盘和鼠标原码
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BYTE			CSD_1SW21_DriveMode_1_ADDR;
#pragma	ioport	CSD_1SW21_DriveMode_2_ADDR:	0xb
BYTE			CSD_1SW21_DriveMode_2_ADDR;
#pragma	ioport	CSD_1SW21_GlobalSelect_ADDR:	0xa
BYTE			CSD_1SW21_GlobalSelect_ADDR;
#pragma	ioport	CSD_1SW21_IntCtrl_0_ADDR:	0x10a
BYTE			CSD_1SW21_IntCtrl_0_ADDR;
#pragma	ioport	CSD_1SW21_IntCtrl_1_ADDR:	0x10b
BYTE			CSD_1SW21_IntCtrl_1_ADDR;
#pragma	ioport	CSD_1SW21_IntEn_ADDR:	0x9
BYTE			CSD_1SW21_IntEn_ADDR;
#define CSD_1SW21_MASK 0x20
#pragma	ioport	CSD_1SW21_MUXBusCtrl_ADDR:	0x1da
BYTE			CSD_1SW21_MUXBusCtrl_ADDR;
// CSD_1SW21 Shadow defines
//   CSD_1SW21_DataShadow define
extern BYTE Port_2_Data_SHADE;
#define CSD_1SW21_DataShadow (*(unsigned char*)&Port_2_Data_SHADE)
// CSD_1SW9 address and mask defines
#pragma	ioport	CSD_1SW9_Data_ADDR:	0x8
BYTE			CSD_1SW9_Data_ADDR;
#pragma	ioport	CSD_1SW9_DriveMode_0_ADDR:	0x108
BYTE			CSD_1SW9_DriveMode_0_ADDR;
#pragma	ioport	CSD_1SW9_DriveMode_1_ADDR:	0x109
BYTE			CSD_1SW9_DriveMode_1_ADDR;
#pragma	ioport	CSD_1SW9_DriveMode_2_ADDR:	0xb
BYTE			CSD_1SW9_DriveMode_2_ADDR;
#pragma	ioport	CSD_1SW9_GlobalSelect_ADDR:	0xa
BYTE			CSD_1SW9_GlobalSelect_ADDR;
#pragma	ioport	CSD_1SW9_IntCtrl_0_ADDR:	0x10a
BYTE			CSD_1SW9_IntCtrl_0_ADDR;
#pragma	ioport	CSD_1SW9_IntCtrl_1_ADDR:	0x10b
BYTE			CSD_1SW9_IntCtrl_1_ADDR;
#pragma	ioport	CSD_1SW9_IntEn_ADDR:	0x9
BYTE			CSD_1SW9_IntEn_ADDR;
#define CSD_1SW9_MASK 0x40
#pragma	ioport	CSD_1SW9_MUXBusCtrl_ADDR:	0x1da
BYTE			CSD_1SW9_MUXBusCtrl_ADDR;
// CSD_1SW9 Shadow defines
//   CSD_1SW9_DataShadow define
extern BYTE Port_2_Data_SHADE;
#define CSD_1SW9_DataShadow (*(unsigned char*)&Port_2_Data_SHADE)
// CSD_1SW27 address and mask defines
#pragma	ioport	CSD_1SW27_Data_ADDR:	0x8
BYTE			CSD_1SW27_Data_ADDR;
#pragma	ioport	CSD_1SW27_DriveMode_0_ADDR:	0x108
BYTE			CSD_1SW27_DriveMode_0_ADDR;
#pragma	ioport	CSD_1SW27_DriveMode_1_ADDR:	0x109
BYTE			CSD_1SW27_DriveMode_1_ADDR;
#pragma	ioport	CSD_1SW27_DriveMode_2_ADDR:	0xb
BYTE			CSD_1SW27_DriveMode_2_ADDR;
#pragma	ioport	CSD_1SW27_GlobalSelect_ADDR:	0xa
BYTE			CSD_1SW27_GlobalSelect_ADDR;
#pragma	ioport	CSD_1SW27_IntCtrl_0_ADDR:	0x10a
BYTE			CSD_1SW27_IntCtrl_0_ADDR;
#pragma	ioport	CSD_1SW27_IntCtrl_1_ADDR:	0x10b
BYTE			CSD_1SW27_IntCtrl_1_ADDR;
#pragma	ioport	CSD_1SW27_IntEn_ADDR:	0x9
BYTE			CSD_1SW27_IntEn_ADDR;
#define CSD_1SW27_MASK 0x80
#pragma	ioport	CSD_1SW27_MUXBusCtrl_ADDR:	0x1da
BYTE			CSD_1SW27_MUXBusCtrl_ADDR;
// CSD_1SW27 Shadow defines
//   CSD_1SW27_DataShadow define
extern BYTE Port_2_Data_SHADE;
#define CSD_1SW27_DataShadow (*(unsigned char*)&Port_2_Data_SHADE)
// CSD_1SW6 address and mask defines
#pragma	ioport	CSD_1SW6_Data_ADDR:	0xc
BYTE			CSD_1SW6_Data_ADDR;
#pragma	ioport	CSD_1SW6_DriveMode_0_ADDR:	0x10c
BYTE			CSD_1SW6_DriveMode_0_ADDR;
#pragma	ioport	CSD_1SW6_DriveMode_1_ADDR:	0x10d
BYTE			CSD_1SW6_DriveMode_1_ADDR;
#pragma	ioport	CSD_1SW6_DriveMode_2_ADDR:	0xf
BYTE			CSD_1SW6_DriveMode_2_ADDR;
#pragma	ioport	CSD_1SW6_GlobalSelect_ADDR:	0xe
BYTE			CSD_1SW6_GlobalSelect_ADDR;
#pragma	ioport	CSD_1SW6_IntCtrl_0_ADDR:	0x10e
BYTE			CSD_1SW6_IntCtrl_0_ADDR;
#pragma	ioport	CSD_1SW6_IntCtrl_1_ADDR:	0x10f
BYTE			CSD_1SW6_IntCtrl_1_ADDR;
#pragma	ioport	CSD_1SW6_IntEn_ADDR:	0xd
BYTE			CSD_1SW6_IntEn_ADDR;
#define CSD_1SW6_MASK 0x1
#pragma	ioport	CSD_1SW6_MUXBusCtrl_ADDR:	0x1db
BYTE			CSD_1SW6_MUXBusCtrl_ADDR;
// CSD_1SW6 Shadow defines
//   CSD_1SW6_DataShadow define
extern BYTE Port_3_Data_SHADE;
#define CSD_1SW6_DataShadow (*(unsigned char*)&Port_3_Data_SHADE)
// CSD_1SW20 address and mask defines
#pragma	ioport	CSD_1SW20_Data_ADDR:	0xc
BYTE			CSD_1SW20_Data_ADDR;
#pragma	ioport	CSD_1SW20_DriveMode_0_ADDR:	0x10c
BYTE			CSD_1SW20_DriveMode_0_ADDR;
#pragma	ioport	CSD_1SW20_DriveMode_1_ADDR:	0x10d
BYTE			CSD_1SW20_DriveMode_1_ADDR;
#pragma	ioport	CSD_1SW20_DriveMode_2_ADDR:	0xf
BYTE			CSD_1SW20_DriveMode_2_ADDR;
#pragma	ioport	CSD_1SW20_GlobalSelect_ADDR:	0xe
BYTE			CSD_1SW20_GlobalSelect_ADDR;
#pragma	ioport	CSD_1SW20_IntCtrl_0_ADDR:	0x10e
BYTE			CSD_1SW20_IntCtrl_0_ADDR;
#pragma	ioport	CSD_1SW20_IntCtrl_1_ADDR:	0x10f
BYTE			CSD_1SW20_IntCtrl_1_ADDR;
#pragma	ioport	CSD_1SW20_IntEn_ADDR:	0xd
BYTE			CSD_1SW20_IntEn_ADDR;
#define CSD_1SW20_MASK 0x2
#pragma	ioport	CSD_1SW20_MUXBusCtrl_ADDR:	0x1db
BYTE			CSD_1SW20_MUXBusCtrl_ADDR;
// CSD_1SW20 Shadow defines
//   CSD_1SW20_DataShadow define
extern BYTE Port_3_Data_SHADE;
#define CSD_1SW20_DataShadow (*(unsigned char*)&Port_3_Data_SHADE)
// CSD_1SW13 address and mask defines
#pragma	ioport	CSD_1SW13_Data_ADDR:	0xc
BYTE			CSD_1SW13_Data_ADDR;
#pragma	ioport	CSD_1SW13_DriveMode_0_ADDR:	0x10c
BYTE			CSD_1SW13_DriveMode_0_ADDR;
#pragma	ioport	CSD_1SW13_DriveMode_1_ADDR:	0x10d
BYTE			CSD_1SW13_DriveMode_1_ADDR;
#pragma	ioport	CSD_1SW13_DriveMode_2_ADDR:	0xf
BYTE			CSD_1SW13_DriveMode_2_ADDR;
#pragma	ioport	CSD_1SW13_GlobalSelect_ADDR:	0xe
BYTE			CSD_1SW13_GlobalSelect_ADDR;
#pragma	ioport	CSD_1SW13_IntCtrl_0_ADDR:	0x10e
BYTE			CSD_1SW13_IntCtrl_0_ADDR;
#pragma	ioport	CSD_1SW13_IntCtrl_1_ADDR:	0x10f
BYTE			CSD_1SW13_IntCtrl_1_ADDR;
#pragma	ioport	CSD_1SW13_IntEn_ADDR:	0xd
BYTE			CSD_1SW13_IntEn_ADDR;
#define CSD_1SW13_MASK 0x4
#pragma	ioport	CSD_1SW13_MUXBusCtrl_ADDR:	0x1db
BYTE			CSD_1SW13_MUXBusCtrl_ADDR;
// CSD_1SW13 Shadow defines
//   CSD_1SW13_DataShadow define
extern BYTE Port_3_Data_SHADE;
#define CSD_1SW13_DataShadow (*(unsigned char*)&Port_3_Data_SHADE)
// CSD_1SW24 address and mask defines
#pragma	ioport	CSD_1SW24_Data_ADDR:	0xc
BYTE			CSD_1SW24_Data_ADDR;
#pragma	ioport	CSD_1SW24_DriveMode_0_ADDR:	0x10c
BYTE			CSD_1SW24_DriveMode_0_ADDR;
#pragma	ioport	CSD_1SW24_DriveMode_1_ADDR:	0x10d
BYTE			CSD_1SW24_DriveMode_1_ADDR;
#pragma	ioport	CSD_1SW24_DriveMode_2_ADDR:	0xf
BYTE			CSD_1SW24_DriveMode_2_ADDR;
#pragma	ioport	CSD_1SW24_GlobalSelect_ADDR:	0xe
BYTE			CSD_1SW24_GlobalSelect_ADDR;
#pragma	ioport	CSD_1SW24_IntCtrl_0_ADDR:	0x10e
BYTE			CSD_1SW24_IntCtrl_0_ADDR;
#pragma	ioport	CSD_1SW24_IntCtrl_1_ADDR:	0x10f
BYTE			CSD_1SW24_IntCtrl_1_ADDR;
#pragma	ioport	CSD_1SW24_IntEn_ADDR:	0xd
BYTE			CSD_1SW24_IntEn_ADDR;
#define CSD_1SW24_MASK 0x8
#pragma	ioport	CSD_1SW24_MUXBusCtrl_ADDR:	0x1db
BYTE			CSD_1SW24_MUXBusCtrl_ADDR;
// CSD_1SW24 Shadow defines
//   CSD_1SW24_DataShadow define
extern BYTE Port_3_Data_SHADE;
#define CSD_1SW24_DataShadow (*(unsigned char*)&Port_3_Data_SHADE)
// CSD_1SW2 address and mask defines
#pragma	ioport	CSD_1SW2_Data_ADDR:	0xc
BYTE			CSD_1SW2_Data_ADDR;
#pragma	ioport	CSD_1SW2_DriveMode_0_ADDR:	0x10c
BYTE			CSD_1SW2_DriveMode_0_ADDR;
#pragma	ioport	CSD_1SW2_DriveMode_1_ADDR:	0x10d
BYTE			CSD_1SW2_DriveMode_1_ADDR;
#pragma	ioport	CSD_1SW2_DriveMode_2_ADDR:	0xf
BYTE			CSD_1SW2_DriveMode_2_ADDR;
#pragma	ioport	CSD_1SW2_GlobalSelect_ADDR:	0xe
BYTE			CSD_1SW2_GlobalSelect_ADDR;
#pragma	ioport	CSD_1SW2_IntCtrl_0_ADDR:	0x10e
BYTE			CSD_1SW2_IntCtrl_0_ADDR;
#pragma	ioport	CSD_1SW2_IntCtrl_1_ADDR:	0x10f
BYTE			CSD_1SW2_IntCtrl_1_ADDR;
#pragma	ioport	CSD_1SW2_IntEn_ADDR:	0xd
BYTE			CSD_1SW2_IntEn_ADDR;
#define CSD_1SW2_MASK 0x10
#pragma	ioport	CSD_1SW2_MUXBusCtrl_ADDR:	0x1db
BYTE			CSD_1SW2_MUXBusCtrl_ADDR;
// CSD_1SW2 Shadow defines
//   CSD_1SW2_DataShadow define
extern BYTE Port_3_Data_SHADE;
#define CSD_1SW2_DataShadow (*(unsigned char*)&Port_3_Data_SHADE)
// CSD_1SW31 address and mask defines
#pragma	ioport	CSD_1SW31_Data_ADDR:	0xc
BYTE			CSD_1SW31_Data_ADDR;
#pragma	ioport	CSD_1SW31_DriveMode_0_ADDR:	0x10c
BYTE			CSD_1SW31_DriveMode_0_ADDR;
#pragma	ioport	CSD_1SW31_DriveMode_1_ADDR:	0x10d
BYTE			CSD_1SW31_DriveMode_1_ADDR;
#pragma	ioport	CSD_1SW31_DriveMode_2_ADDR:	0xf
BYTE			CSD_1SW31_DriveMode_2_ADDR;
#pragma	ioport	CSD_1SW31_GlobalSelect_ADDR:	0xe
BYTE			CSD_1SW31_GlobalSelect_ADDR;
#pragma	ioport	CSD_1SW31_IntCtrl_0_ADDR:	0x10e
BYTE			CSD_1SW31_IntCtrl_0_ADDR;
#pragma	ioport	CSD_1SW31_IntCtrl_1_ADDR:	0x10f
BYTE			CSD_1SW31_IntCtrl_1_ADDR;
#pragma	ioport	CSD_1SW31_IntEn_ADDR:	0xd
BYTE			CSD_1SW31_IntEn_ADDR;
#define CSD_1SW31_MASK 0x20
#pragma	ioport	CSD_1SW31_MUXBusCtrl_ADDR:	0x1db
BYTE			CSD_1SW31_MUXBusCtrl_ADDR;
// CSD_1SW31 Shadow defines
//   CSD_1SW31_DataShadow define
extern BYTE Port_3_Data_SHADE;
#define CSD_1SW31_DataShadow (*(unsigned char*)&Port_3_Data_SHADE)
// CSD_1SW7 address and mask defines
#pragma	ioport	CSD_1SW7_Data_ADDR:	0xc
BYTE			CSD_1SW7_Data_ADDR;
#pragma	ioport	CSD_1SW7_DriveMode_0_ADDR:	0x10c
BYTE			CSD_1SW7_DriveMode_0_ADDR;
#pragma	ioport	CSD_1SW7_DriveMode_1_ADDR:	0x10d
BYTE			CSD_1SW7_DriveMode_1_ADDR;
#pragma	ioport	CSD_1SW7_DriveMode_2_ADDR:	0xf
BYTE			CSD_1SW7_DriveMode_2_ADDR;
#pragma	ioport	CSD_1SW7_GlobalSelect_ADDR:	0xe
BYTE			CSD_1SW7_GlobalSelect_ADDR;
#pragma	ioport	CSD_1SW7_IntCtrl_0_ADDR:	0x10e
BYTE			CSD_1SW7_IntCtrl_0_ADDR;
#pragma	ioport	CSD_1SW7_IntCtrl_1_ADDR:	0x10f
BYTE			CSD_1SW7_IntCtrl_1_ADDR;
#pragma	ioport	CSD_1SW7_IntEn_ADDR:	0xd
BYTE			CSD_1SW7_IntEn_ADDR;
#define CSD_1SW7_MASK 0x40
#pragma	ioport	CSD_1SW7_MUXBusCtrl_ADDR:	0x1db
BYTE			CSD_1SW7_MUXBusCtrl_ADDR;
// CSD_1SW7 Shadow defines
//   CSD_1SW7_DataShadow define
extern BYTE Port_3_Data_SHADE;
#define CSD_1SW7_DataShadow (*(unsigned char*)&Port_3_Data_SHADE)
// CSD_1SW25 address and mask defines
#pragma	ioport	CSD_1SW25_Data_ADDR:	0xc
BYTE			CSD_1SW25_Data_ADDR;
#pragma	ioport	CSD_1SW25_DriveMode_0_ADDR:	0x10c
BYTE			CSD_1SW25_DriveMode_0_ADDR;
#pragma	ioport	CSD_1SW25_DriveMode_1_ADDR:	0x10d
BYTE			CSD_1SW25_DriveMode_1_ADDR;
#pragma	ioport	CSD_1SW25_DriveMode_2_ADDR:	0xf
BYTE			CSD_1SW25_DriveMode_2_ADDR;
#pragma	ioport	CSD_1SW25_GlobalSelect_ADDR:	0xe
BYTE			CSD_1SW25_GlobalSelect_ADDR;
#pragma	ioport	CSD_1SW25_IntCtrl_0_ADDR:	0x10e
BYTE			CSD_1SW25_IntCtrl_0_ADDR;
#pragma	ioport	CSD_1SW25_IntCtrl_1_ADDR:	0x10f
BYTE			CSD_1SW25_IntCtrl_1_ADDR;
#pragma	ioport	CSD_1SW25_IntEn_ADDR:	0xd
BYTE			CSD_1SW25_IntEn_ADDR;
#define CSD_1SW25_MASK 0x80
#pragma	ioport	CSD_1SW25_MUXBusCtrl_ADDR:	0x1db
BYTE			CSD_1SW25_MUXBusCtrl_ADDR;
// CSD_1SW25 Shadow defines
//   CSD_1SW25_DataShadow define
extern BYTE Port_3_Data_SHADE;
#define CSD_1SW25_DataShadow (*(unsigned char*)&Port_3_Data_SHADE)
// CSD_1SW14 address and mask defines
#pragma	ioport	CSD_1SW14_Data_ADDR:	0x10
BYTE			CSD_1SW14_Data_ADDR;
#pragma	ioport	CSD_1SW14_DriveMode_0_ADDR:	0x110
BYTE			CSD_1SW14_DriveMode_0_ADDR;
#pragma	ioport	CSD_1SW14_DriveMode_1_ADDR:	0x111
BYTE			CSD_1SW14_DriveMode_1_ADDR;
#pragma	ioport	CSD_1SW14_DriveMode_2_ADDR:	0x13
BYTE			CSD_1SW14_DriveMode_2_ADDR;
#pragma	ioport	CSD_1SW14_GlobalSelect_ADDR:	0x12
BYTE			CSD_1SW14_GlobalSelect_ADDR;
#pragma	ioport	CSD_1SW14_IntCtrl_0_ADDR:	0x112
BYTE			CSD_1SW14_IntCtrl_0_ADDR;
#pragma	ioport	CSD_1SW14_IntCtrl_1_ADDR:	0x113
BYTE			CSD_1SW14_IntCtrl_1_ADDR;
#pragma	ioport	CSD_1SW14_IntEn_ADDR:	0x11
BYTE			CSD_1SW14_IntEn_ADDR;
#define CSD_1SW14_MASK 0x1
#pragma	ioport	CSD_1SW14_MUXBusCtrl_ADDR:	0x1ec
BYTE			CSD_1SW14_MUXBusCtrl_ADDR;
// CSD_1SW14 Shadow defines
//   CSD_1SW14_DataShadow define
extern BYTE Port_4_Data_SHADE;
#define CSD_1SW14_DataShadow (*(unsigned char*)&Port_4_Data_SHADE)
// CSD_1SW32 address and mask defines
#pragma	ioport	CSD_1SW32_Data_ADDR:	0x10
BYTE			CSD_1SW32_Data_ADDR;
#pragma	ioport	CSD_1SW32_DriveMode_0_ADDR:	0x110
BYTE			CSD_1SW32_DriveMode_0_ADDR;
#pragma	ioport	CSD_1SW32_DriveMode_1_ADDR:	0x111
BYTE			CSD_1SW32_DriveMode_1_ADDR;
#pragma	ioport	CSD_1SW32_DriveMode_2_ADDR:	0x13
BYTE			CSD_1SW32_DriveMode_2_ADDR;
#pragma	ioport	CSD_1SW32_GlobalSelect_ADDR:	0x12
BYTE			CSD_1SW32_GlobalSelect_ADDR;
#pragma	ioport	CSD_1SW32_IntCtrl_0_ADDR:	0x112
BYTE			CSD_1SW32_IntCtrl_0_ADDR;
#pragma	ioport	CSD_1SW32_IntCtrl_1_ADDR:	0x113
BYTE			CSD_1SW32_IntCtrl_1_ADDR;
#pragma	ioport	CSD_1SW32_IntEn_ADDR:	0x11
BYTE			CSD_1SW32_IntEn_ADDR;
#define CSD_1SW32_MASK 0x2
#pragma	ioport	CSD_1SW32_MUXBusCtrl_ADDR:	0x1ec
BYTE			CSD_1SW32_MUXBusCtrl_ADDR;
// CSD_1SW32 Shadow defines
//   CSD_1SW32_DataShadow define
extern BYTE Port_4_Data_SHADE;
#define CSD_1SW32_DataShadow (*(unsigned char*)&Port_4_Data_SHADE)
// CSD_1SW0 address and mask defines
#pragma	ioport	CSD_1SW0_Data_ADDR:	0x10
BYTE			CSD_1SW0_Data_ADDR;
#pragma	ioport	CSD_1SW0_DriveMode_0_ADDR:	0x110
BYTE			CSD_1SW0_DriveMode_0_ADDR;
#pragma	ioport	CSD_1SW0_DriveMode_1_ADDR:	0x111
BYTE			CSD_1SW0_DriveMode_1_ADDR;
#pragma	ioport	CSD_1SW0_DriveMode_2_ADDR:	0x13
BYTE			CSD_1SW0_DriveMode_2_ADDR;
#pragma	ioport	CSD_1SW0_GlobalSelect_ADDR:	0x12
BYTE			CSD_1SW0_GlobalSelect_ADDR;
#pragma	ioport	CSD_1SW0_IntCtrl_0_ADDR:	0x112
BYTE			CSD_1SW0_IntCtrl_0_ADDR;
#pragma	ioport	CSD_1SW0_IntCtrl_1_ADDR:	0x113
BYTE			CSD_1SW0_IntCtrl_1_ADDR;
#pragma	ioport	CSD_1SW0_IntEn_ADDR:	0x11

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