📄 psocgpioint.h
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/******************************************************************************
* Generated by PSoC Designer ver 4.4 b1884 : 14 Jan, 2007
******************************************************************************/
#include <m8c.h>
// CSD_1SW16 address and mask defines
#pragma ioport CSD_1SW16_Data_ADDR: 0x0
BYTE CSD_1SW16_Data_ADDR;
#pragma ioport CSD_1SW16_DriveMode_0_ADDR: 0x100
BYTE CSD_1SW16_DriveMode_0_ADDR;
#pragma ioport CSD_1SW16_DriveMode_1_ADDR: 0x101
BYTE CSD_1SW16_DriveMode_1_ADDR;
#pragma ioport CSD_1SW16_DriveMode_2_ADDR: 0x3
BYTE CSD_1SW16_DriveMode_2_ADDR;
#pragma ioport CSD_1SW16_GlobalSelect_ADDR: 0x2
BYTE CSD_1SW16_GlobalSelect_ADDR;
#pragma ioport CSD_1SW16_IntCtrl_0_ADDR: 0x102
BYTE CSD_1SW16_IntCtrl_0_ADDR;
#pragma ioport CSD_1SW16_IntCtrl_1_ADDR: 0x103
BYTE CSD_1SW16_IntCtrl_1_ADDR;
#pragma ioport CSD_1SW16_IntEn_ADDR: 0x1
BYTE CSD_1SW16_IntEn_ADDR;
#define CSD_1SW16_MASK 0x1
#pragma ioport CSD_1SW16_MUXBusCtrl_ADDR: 0x1d8
BYTE CSD_1SW16_MUXBusCtrl_ADDR;
// CSD_1SW16 Shadow defines
// CSD_1SW16_DataShadow define
extern BYTE Port_0_Data_SHADE;
#define CSD_1SW16_DataShadow (*(unsigned char*)&Port_0_Data_SHADE)
// CSD_1SW34 address and mask defines
#pragma ioport CSD_1SW34_Data_ADDR: 0x0
BYTE CSD_1SW34_Data_ADDR;
#pragma ioport CSD_1SW34_DriveMode_0_ADDR: 0x100
BYTE CSD_1SW34_DriveMode_0_ADDR;
#pragma ioport CSD_1SW34_DriveMode_1_ADDR: 0x101
BYTE CSD_1SW34_DriveMode_1_ADDR;
#pragma ioport CSD_1SW34_DriveMode_2_ADDR: 0x3
BYTE CSD_1SW34_DriveMode_2_ADDR;
#pragma ioport CSD_1SW34_GlobalSelect_ADDR: 0x2
BYTE CSD_1SW34_GlobalSelect_ADDR;
#pragma ioport CSD_1SW34_IntCtrl_0_ADDR: 0x102
BYTE CSD_1SW34_IntCtrl_0_ADDR;
#pragma ioport CSD_1SW34_IntCtrl_1_ADDR: 0x103
BYTE CSD_1SW34_IntCtrl_1_ADDR;
#pragma ioport CSD_1SW34_IntEn_ADDR: 0x1
BYTE CSD_1SW34_IntEn_ADDR;
#define CSD_1SW34_MASK 0x2
#pragma ioport CSD_1SW34_MUXBusCtrl_ADDR: 0x1d8
BYTE CSD_1SW34_MUXBusCtrl_ADDR;
// CSD_1SW34 Shadow defines
// CSD_1SW34_DataShadow define
extern BYTE Port_0_Data_SHADE;
#define CSD_1SW34_DataShadow (*(unsigned char*)&Port_0_Data_SHADE)
// CSD_1SW4 address and mask defines
#pragma ioport CSD_1SW4_Data_ADDR: 0x0
BYTE CSD_1SW4_Data_ADDR;
#pragma ioport CSD_1SW4_DriveMode_0_ADDR: 0x100
BYTE CSD_1SW4_DriveMode_0_ADDR;
#pragma ioport CSD_1SW4_DriveMode_1_ADDR: 0x101
BYTE CSD_1SW4_DriveMode_1_ADDR;
#pragma ioport CSD_1SW4_DriveMode_2_ADDR: 0x3
BYTE CSD_1SW4_DriveMode_2_ADDR;
#pragma ioport CSD_1SW4_GlobalSelect_ADDR: 0x2
BYTE CSD_1SW4_GlobalSelect_ADDR;
#pragma ioport CSD_1SW4_IntCtrl_0_ADDR: 0x102
BYTE CSD_1SW4_IntCtrl_0_ADDR;
#pragma ioport CSD_1SW4_IntCtrl_1_ADDR: 0x103
BYTE CSD_1SW4_IntCtrl_1_ADDR;
#pragma ioport CSD_1SW4_IntEn_ADDR: 0x1
BYTE CSD_1SW4_IntEn_ADDR;
#define CSD_1SW4_MASK 0x4
#pragma ioport CSD_1SW4_MUXBusCtrl_ADDR: 0x1d8
BYTE CSD_1SW4_MUXBusCtrl_ADDR;
// CSD_1SW4 Shadow defines
// CSD_1SW4_DataShadow define
extern BYTE Port_0_Data_SHADE;
#define CSD_1SW4_DataShadow (*(unsigned char*)&Port_0_Data_SHADE)
// CSD_1SW22 address and mask defines
#pragma ioport CSD_1SW22_Data_ADDR: 0x0
BYTE CSD_1SW22_Data_ADDR;
#pragma ioport CSD_1SW22_DriveMode_0_ADDR: 0x100
BYTE CSD_1SW22_DriveMode_0_ADDR;
#pragma ioport CSD_1SW22_DriveMode_1_ADDR: 0x101
BYTE CSD_1SW22_DriveMode_1_ADDR;
#pragma ioport CSD_1SW22_DriveMode_2_ADDR: 0x3
BYTE CSD_1SW22_DriveMode_2_ADDR;
#pragma ioport CSD_1SW22_GlobalSelect_ADDR: 0x2
BYTE CSD_1SW22_GlobalSelect_ADDR;
#pragma ioport CSD_1SW22_IntCtrl_0_ADDR: 0x102
BYTE CSD_1SW22_IntCtrl_0_ADDR;
#pragma ioport CSD_1SW22_IntCtrl_1_ADDR: 0x103
BYTE CSD_1SW22_IntCtrl_1_ADDR;
#pragma ioport CSD_1SW22_IntEn_ADDR: 0x1
BYTE CSD_1SW22_IntEn_ADDR;
#define CSD_1SW22_MASK 0x8
#pragma ioport CSD_1SW22_MUXBusCtrl_ADDR: 0x1d8
BYTE CSD_1SW22_MUXBusCtrl_ADDR;
// CSD_1SW22 Shadow defines
// CSD_1SW22_DataShadow define
extern BYTE Port_0_Data_SHADE;
#define CSD_1SW22_DataShadow (*(unsigned char*)&Port_0_Data_SHADE)
// CSD_1SW10 address and mask defines
#pragma ioport CSD_1SW10_Data_ADDR: 0x0
BYTE CSD_1SW10_Data_ADDR;
#pragma ioport CSD_1SW10_DriveMode_0_ADDR: 0x100
BYTE CSD_1SW10_DriveMode_0_ADDR;
#pragma ioport CSD_1SW10_DriveMode_1_ADDR: 0x101
BYTE CSD_1SW10_DriveMode_1_ADDR;
#pragma ioport CSD_1SW10_DriveMode_2_ADDR: 0x3
BYTE CSD_1SW10_DriveMode_2_ADDR;
#pragma ioport CSD_1SW10_GlobalSelect_ADDR: 0x2
BYTE CSD_1SW10_GlobalSelect_ADDR;
#pragma ioport CSD_1SW10_IntCtrl_0_ADDR: 0x102
BYTE CSD_1SW10_IntCtrl_0_ADDR;
#pragma ioport CSD_1SW10_IntCtrl_1_ADDR: 0x103
BYTE CSD_1SW10_IntCtrl_1_ADDR;
#pragma ioport CSD_1SW10_IntEn_ADDR: 0x1
BYTE CSD_1SW10_IntEn_ADDR;
#define CSD_1SW10_MASK 0x10
#pragma ioport CSD_1SW10_MUXBusCtrl_ADDR: 0x1d8
BYTE CSD_1SW10_MUXBusCtrl_ADDR;
// CSD_1SW10 Shadow defines
// CSD_1SW10_DataShadow define
extern BYTE Port_0_Data_SHADE;
#define CSD_1SW10_DataShadow (*(unsigned char*)&Port_0_Data_SHADE)
// CSD_1SW28 address and mask defines
#pragma ioport CSD_1SW28_Data_ADDR: 0x0
BYTE CSD_1SW28_Data_ADDR;
#pragma ioport CSD_1SW28_DriveMode_0_ADDR: 0x100
BYTE CSD_1SW28_DriveMode_0_ADDR;
#pragma ioport CSD_1SW28_DriveMode_1_ADDR: 0x101
BYTE CSD_1SW28_DriveMode_1_ADDR;
#pragma ioport CSD_1SW28_DriveMode_2_ADDR: 0x3
BYTE CSD_1SW28_DriveMode_2_ADDR;
#pragma ioport CSD_1SW28_GlobalSelect_ADDR: 0x2
BYTE CSD_1SW28_GlobalSelect_ADDR;
#pragma ioport CSD_1SW28_IntCtrl_0_ADDR: 0x102
BYTE CSD_1SW28_IntCtrl_0_ADDR;
#pragma ioport CSD_1SW28_IntCtrl_1_ADDR: 0x103
BYTE CSD_1SW28_IntCtrl_1_ADDR;
#pragma ioport CSD_1SW28_IntEn_ADDR: 0x1
BYTE CSD_1SW28_IntEn_ADDR;
#define CSD_1SW28_MASK 0x20
#pragma ioport CSD_1SW28_MUXBusCtrl_ADDR: 0x1d8
BYTE CSD_1SW28_MUXBusCtrl_ADDR;
// CSD_1SW28 Shadow defines
// CSD_1SW28_DataShadow define
extern BYTE Port_0_Data_SHADE;
#define CSD_1SW28_DataShadow (*(unsigned char*)&Port_0_Data_SHADE)
// CSD_1SW17 address and mask defines
#pragma ioport CSD_1SW17_Data_ADDR: 0x0
BYTE CSD_1SW17_Data_ADDR;
#pragma ioport CSD_1SW17_DriveMode_0_ADDR: 0x100
BYTE CSD_1SW17_DriveMode_0_ADDR;
#pragma ioport CSD_1SW17_DriveMode_1_ADDR: 0x101
BYTE CSD_1SW17_DriveMode_1_ADDR;
#pragma ioport CSD_1SW17_DriveMode_2_ADDR: 0x3
BYTE CSD_1SW17_DriveMode_2_ADDR;
#pragma ioport CSD_1SW17_GlobalSelect_ADDR: 0x2
BYTE CSD_1SW17_GlobalSelect_ADDR;
#pragma ioport CSD_1SW17_IntCtrl_0_ADDR: 0x102
BYTE CSD_1SW17_IntCtrl_0_ADDR;
#pragma ioport CSD_1SW17_IntCtrl_1_ADDR: 0x103
BYTE CSD_1SW17_IntCtrl_1_ADDR;
#pragma ioport CSD_1SW17_IntEn_ADDR: 0x1
BYTE CSD_1SW17_IntEn_ADDR;
#define CSD_1SW17_MASK 0x40
#pragma ioport CSD_1SW17_MUXBusCtrl_ADDR: 0x1d8
BYTE CSD_1SW17_MUXBusCtrl_ADDR;
// CSD_1SW17 Shadow defines
// CSD_1SW17_DataShadow define
extern BYTE Port_0_Data_SHADE;
#define CSD_1SW17_DataShadow (*(unsigned char*)&Port_0_Data_SHADE)
// CSD_1Capacitor address and mask defines
#pragma ioport CSD_1Capacitor_Data_ADDR: 0x0
BYTE CSD_1Capacitor_Data_ADDR;
#pragma ioport CSD_1Capacitor_DriveMode_0_ADDR: 0x100
BYTE CSD_1Capacitor_DriveMode_0_ADDR;
#pragma ioport CSD_1Capacitor_DriveMode_1_ADDR: 0x101
BYTE CSD_1Capacitor_DriveMode_1_ADDR;
#pragma ioport CSD_1Capacitor_DriveMode_2_ADDR: 0x3
BYTE CSD_1Capacitor_DriveMode_2_ADDR;
#pragma ioport CSD_1Capacitor_GlobalSelect_ADDR: 0x2
BYTE CSD_1Capacitor_GlobalSelect_ADDR;
#pragma ioport CSD_1Capacitor_IntCtrl_0_ADDR: 0x102
BYTE CSD_1Capacitor_IntCtrl_0_ADDR;
#pragma ioport CSD_1Capacitor_IntCtrl_1_ADDR: 0x103
BYTE CSD_1Capacitor_IntCtrl_1_ADDR;
#pragma ioport CSD_1Capacitor_IntEn_ADDR: 0x1
BYTE CSD_1Capacitor_IntEn_ADDR;
#define CSD_1Capacitor_MASK 0x80
#pragma ioport CSD_1Capacitor_MUXBusCtrl_ADDR: 0x1d8
BYTE CSD_1Capacitor_MUXBusCtrl_ADDR;
// CSD_1Capacitor Shadow defines
// CSD_1Capacitor_DataShadow define
extern BYTE Port_0_Data_SHADE;
#define CSD_1Capacitor_DataShadow (*(unsigned char*)&Port_0_Data_SHADE)
// LED_ShiftCAPPin address and mask defines
#pragma ioport LED_ShiftCAPPin_Data_ADDR: 0x4
BYTE LED_ShiftCAPPin_Data_ADDR;
#pragma ioport LED_ShiftCAPPin_DriveMode_0_ADDR: 0x104
BYTE LED_ShiftCAPPin_DriveMode_0_ADDR;
#pragma ioport LED_ShiftCAPPin_DriveMode_1_ADDR: 0x105
BYTE LED_ShiftCAPPin_DriveMode_1_ADDR;
#pragma ioport LED_ShiftCAPPin_DriveMode_2_ADDR: 0x7
BYTE LED_ShiftCAPPin_DriveMode_2_ADDR;
#pragma ioport LED_ShiftCAPPin_GlobalSelect_ADDR: 0x6
BYTE LED_ShiftCAPPin_GlobalSelect_ADDR;
#pragma ioport LED_ShiftCAPPin_IntCtrl_0_ADDR: 0x106
BYTE LED_ShiftCAPPin_IntCtrl_0_ADDR;
#pragma ioport LED_ShiftCAPPin_IntCtrl_1_ADDR: 0x107
BYTE LED_ShiftCAPPin_IntCtrl_1_ADDR;
#pragma ioport LED_ShiftCAPPin_IntEn_ADDR: 0x5
BYTE LED_ShiftCAPPin_IntEn_ADDR;
#define LED_ShiftCAPPin_MASK 0x10
#pragma ioport LED_ShiftCAPPin_MUXBusCtrl_ADDR: 0x1d9
BYTE LED_ShiftCAPPin_MUXBusCtrl_ADDR;
// LED_ShiftCAPPin Shadow defines
// LED_ShiftCAPPin_DataShadow define
extern BYTE Port_1_Data_SHADE;
#define LED_ShiftCAPPin_DataShadow (*(unsigned char*)&Port_1_Data_SHADE)
// CSD_1Resistor address and mask defines
#pragma ioport CSD_1Resistor_Data_ADDR: 0x4
BYTE CSD_1Resistor_Data_ADDR;
#pragma ioport CSD_1Resistor_DriveMode_0_ADDR: 0x104
BYTE CSD_1Resistor_DriveMode_0_ADDR;
#pragma ioport CSD_1Resistor_DriveMode_1_ADDR: 0x105
BYTE CSD_1Resistor_DriveMode_1_ADDR;
#pragma ioport CSD_1Resistor_DriveMode_2_ADDR: 0x7
BYTE CSD_1Resistor_DriveMode_2_ADDR;
#pragma ioport CSD_1Resistor_GlobalSelect_ADDR: 0x6
BYTE CSD_1Resistor_GlobalSelect_ADDR;
#pragma ioport CSD_1Resistor_IntCtrl_0_ADDR: 0x106
BYTE CSD_1Resistor_IntCtrl_0_ADDR;
#pragma ioport CSD_1Resistor_IntCtrl_1_ADDR: 0x107
BYTE CSD_1Resistor_IntCtrl_1_ADDR;
#pragma ioport CSD_1Resistor_IntEn_ADDR: 0x5
BYTE CSD_1Resistor_IntEn_ADDR;
#define CSD_1Resistor_MASK 0x20
#pragma ioport CSD_1Resistor_MUXBusCtrl_ADDR: 0x1d9
BYTE CSD_1Resistor_MUXBusCtrl_ADDR;
// CSD_1Resistor Shadow defines
// CSD_1Resistor_DataShadow define
extern BYTE Port_1_Data_SHADE;
#define CSD_1Resistor_DataShadow (*(unsigned char*)&Port_1_Data_SHADE)
// BeepPin address and mask defines
#pragma ioport BeepPin_Data_ADDR: 0x4
BYTE BeepPin_Data_ADDR;
#pragma ioport BeepPin_DriveMode_0_ADDR: 0x104
BYTE BeepPin_DriveMode_0_ADDR;
#pragma ioport BeepPin_DriveMode_1_ADDR: 0x105
BYTE BeepPin_DriveMode_1_ADDR;
#pragma ioport BeepPin_DriveMode_2_ADDR: 0x7
BYTE BeepPin_DriveMode_2_ADDR;
#pragma ioport BeepPin_GlobalSelect_ADDR: 0x6
BYTE BeepPin_GlobalSelect_ADDR;
#pragma ioport BeepPin_IntCtrl_0_ADDR: 0x106
BYTE BeepPin_IntCtrl_0_ADDR;
#pragma ioport BeepPin_IntCtrl_1_ADDR: 0x107
BYTE BeepPin_IntCtrl_1_ADDR;
#pragma ioport BeepPin_IntEn_ADDR: 0x5
BYTE BeepPin_IntEn_ADDR;
#define BeepPin_MASK 0x40
#pragma ioport BeepPin_MUXBusCtrl_ADDR: 0x1d9
BYTE BeepPin_MUXBusCtrl_ADDR;
// BeepPin Shadow defines
// BeepPin_DataShadow define
extern BYTE Port_1_Data_SHADE;
#define BeepPin_DataShadow (*(unsigned char*)&Port_1_Data_SHADE)
// CSD_1SW35 address and mask defines
#pragma ioport CSD_1SW35_Data_ADDR: 0x4
BYTE CSD_1SW35_Data_ADDR;
#pragma ioport CSD_1SW35_DriveMode_0_ADDR: 0x104
BYTE CSD_1SW35_DriveMode_0_ADDR;
#pragma ioport CSD_1SW35_DriveMode_1_ADDR: 0x105
BYTE CSD_1SW35_DriveMode_1_ADDR;
#pragma ioport CSD_1SW35_DriveMode_2_ADDR: 0x7
BYTE CSD_1SW35_DriveMode_2_ADDR;
#pragma ioport CSD_1SW35_GlobalSelect_ADDR: 0x6
BYTE CSD_1SW35_GlobalSelect_ADDR;
#pragma ioport CSD_1SW35_IntCtrl_0_ADDR: 0x106
BYTE CSD_1SW35_IntCtrl_0_ADDR;
#pragma ioport CSD_1SW35_IntCtrl_1_ADDR: 0x107
BYTE CSD_1SW35_IntCtrl_1_ADDR;
#pragma ioport CSD_1SW35_IntEn_ADDR: 0x5
BYTE CSD_1SW35_IntEn_ADDR;
#define CSD_1SW35_MASK 0x80
#pragma ioport CSD_1SW35_MUXBusCtrl_ADDR: 0x1d9
BYTE CSD_1SW35_MUXBusCtrl_ADDR;
// CSD_1SW35 Shadow defines
// CSD_1SW35_DataShadow define
extern BYTE Port_1_Data_SHADE;
#define CSD_1SW35_DataShadow (*(unsigned char*)&Port_1_Data_SHADE)
// CSD_1SW3 address and mask defines
#pragma ioport CSD_1SW3_Data_ADDR: 0x8
BYTE CSD_1SW3_Data_ADDR;
#pragma ioport CSD_1SW3_DriveMode_0_ADDR: 0x108
BYTE CSD_1SW3_DriveMode_0_ADDR;
#pragma ioport CSD_1SW3_DriveMode_1_ADDR: 0x109
BYTE CSD_1SW3_DriveMode_1_ADDR;
#pragma ioport CSD_1SW3_DriveMode_2_ADDR: 0xb
BYTE CSD_1SW3_DriveMode_2_ADDR;
#pragma ioport CSD_1SW3_GlobalSelect_ADDR: 0xa
BYTE CSD_1SW3_GlobalSelect_ADDR;
#pragma ioport CSD_1SW3_IntCtrl_0_ADDR: 0x10a
BYTE CSD_1SW3_IntCtrl_0_ADDR;
#pragma ioport CSD_1SW3_IntCtrl_1_ADDR: 0x10b
BYTE CSD_1SW3_IntCtrl_1_ADDR;
#pragma ioport CSD_1SW3_IntEn_ADDR: 0x9
BYTE CSD_1SW3_IntEn_ADDR;
#define CSD_1SW3_MASK 0x10
#pragma ioport CSD_1SW3_MUXBusCtrl_ADDR: 0x1da
BYTE CSD_1SW3_MUXBusCtrl_ADDR;
// CSD_1SW3 Shadow defines
// CSD_1SW3_DataShadow define
extern BYTE Port_2_Data_SHADE;
#define CSD_1SW3_DataShadow (*(unsigned char*)&Port_2_Data_SHADE)
// CSD_1SW21 address and mask defines
#pragma ioport CSD_1SW21_Data_ADDR: 0x8
BYTE CSD_1SW21_Data_ADDR;
#pragma ioport CSD_1SW21_DriveMode_0_ADDR: 0x108
BYTE CSD_1SW21_DriveMode_0_ADDR;
#pragma ioport CSD_1SW21_DriveMode_1_ADDR: 0x109
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