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cypresscy74294ic键盘和鼠标原码

	mov		reg[Port_4_Data], [Port_4_Data_SHADE]
endm
;   SetCSD_1SW0_Data macro
macro ClearCSD_1SW0_Data
	and		[Port_4_Data_SHADE], ~4h
	mov		reg[Port_4_Data], [Port_4_Data_SHADE]
endm

; CSD_1SW18 address and mask equates
CSD_1SW18_Data_ADDR:	equ	10h
CSD_1SW18_DriveMode_0_ADDR:	equ	110h
CSD_1SW18_DriveMode_1_ADDR:	equ	111h
CSD_1SW18_DriveMode_2_ADDR:	equ	13h
CSD_1SW18_GlobalSelect_ADDR:	equ	12h
CSD_1SW18_IntCtrl_0_ADDR:	equ	112h
CSD_1SW18_IntCtrl_1_ADDR:	equ	113h
CSD_1SW18_IntEn_ADDR:	equ	11h
CSD_1SW18_MASK:	equ	8h
CSD_1SW18_MUXBusCtrl_ADDR:	equ	1ech
; CSD_1SW18_Data access macros
;   GetCSD_1SW18_Data macro, return in a
macro GetCSD_1SW18_Data
	mov		a,[Port_4_Data_SHADE]
	and		a, 8h
endm
;   SetCSD_1SW18_Data macro
macro SetCSD_1SW18_Data
	or		[Port_4_Data_SHADE], 8h
	mov		reg[Port_4_Data], [Port_4_Data_SHADE]
endm
;   SetCSD_1SW18_Data macro
macro ClearCSD_1SW18_Data
	and		[Port_4_Data_SHADE], ~8h
	mov		reg[Port_4_Data], [Port_4_Data_SHADE]
endm

; CSD_1SW8 address and mask equates
CSD_1SW8_Data_ADDR:	equ	10h
CSD_1SW8_DriveMode_0_ADDR:	equ	110h
CSD_1SW8_DriveMode_1_ADDR:	equ	111h
CSD_1SW8_DriveMode_2_ADDR:	equ	13h
CSD_1SW8_GlobalSelect_ADDR:	equ	12h
CSD_1SW8_IntCtrl_0_ADDR:	equ	112h
CSD_1SW8_IntCtrl_1_ADDR:	equ	113h
CSD_1SW8_IntEn_ADDR:	equ	11h
CSD_1SW8_MASK:	equ	10h
CSD_1SW8_MUXBusCtrl_ADDR:	equ	1ech
; CSD_1SW8_Data access macros
;   GetCSD_1SW8_Data macro, return in a
macro GetCSD_1SW8_Data
	mov		a,[Port_4_Data_SHADE]
	and		a, 10h
endm
;   SetCSD_1SW8_Data macro
macro SetCSD_1SW8_Data
	or		[Port_4_Data_SHADE], 10h
	mov		reg[Port_4_Data], [Port_4_Data_SHADE]
endm
;   SetCSD_1SW8_Data macro
macro ClearCSD_1SW8_Data
	and		[Port_4_Data_SHADE], ~10h
	mov		reg[Port_4_Data], [Port_4_Data_SHADE]
endm

; CSD_1SW26 address and mask equates
CSD_1SW26_Data_ADDR:	equ	10h
CSD_1SW26_DriveMode_0_ADDR:	equ	110h
CSD_1SW26_DriveMode_1_ADDR:	equ	111h
CSD_1SW26_DriveMode_2_ADDR:	equ	13h
CSD_1SW26_GlobalSelect_ADDR:	equ	12h
CSD_1SW26_IntCtrl_0_ADDR:	equ	112h
CSD_1SW26_IntCtrl_1_ADDR:	equ	113h
CSD_1SW26_IntEn_ADDR:	equ	11h
CSD_1SW26_MASK:	equ	20h
CSD_1SW26_MUXBusCtrl_ADDR:	equ	1ech
; CSD_1SW26_Data access macros
;   GetCSD_1SW26_Data macro, return in a
macro GetCSD_1SW26_Data
	mov		a,[Port_4_Data_SHADE]
	and		a, 20h
endm
;   SetCSD_1SW26_Data macro
macro SetCSD_1SW26_Data
	or		[Port_4_Data_SHADE], 20h
	mov		reg[Port_4_Data], [Port_4_Data_SHADE]
endm
;   SetCSD_1SW26_Data macro
macro ClearCSD_1SW26_Data
	and		[Port_4_Data_SHADE], ~20h
	mov		reg[Port_4_Data], [Port_4_Data_SHADE]
endm

; CSD_1SW15 address and mask equates
CSD_1SW15_Data_ADDR:	equ	10h
CSD_1SW15_DriveMode_0_ADDR:	equ	110h
CSD_1SW15_DriveMode_1_ADDR:	equ	111h
CSD_1SW15_DriveMode_2_ADDR:	equ	13h
CSD_1SW15_GlobalSelect_ADDR:	equ	12h
CSD_1SW15_IntCtrl_0_ADDR:	equ	112h
CSD_1SW15_IntCtrl_1_ADDR:	equ	113h
CSD_1SW15_IntEn_ADDR:	equ	11h
CSD_1SW15_MASK:	equ	40h
CSD_1SW15_MUXBusCtrl_ADDR:	equ	1ech
; CSD_1SW15_Data access macros
;   GetCSD_1SW15_Data macro, return in a
macro GetCSD_1SW15_Data
	mov		a,[Port_4_Data_SHADE]
	and		a, 40h
endm
;   SetCSD_1SW15_Data macro
macro SetCSD_1SW15_Data
	or		[Port_4_Data_SHADE], 40h
	mov		reg[Port_4_Data], [Port_4_Data_SHADE]
endm
;   SetCSD_1SW15_Data macro
macro ClearCSD_1SW15_Data
	and		[Port_4_Data_SHADE], ~40h
	mov		reg[Port_4_Data], [Port_4_Data_SHADE]
endm

; CSD_1SW33 address and mask equates
CSD_1SW33_Data_ADDR:	equ	10h
CSD_1SW33_DriveMode_0_ADDR:	equ	110h
CSD_1SW33_DriveMode_1_ADDR:	equ	111h
CSD_1SW33_DriveMode_2_ADDR:	equ	13h
CSD_1SW33_GlobalSelect_ADDR:	equ	12h
CSD_1SW33_IntCtrl_0_ADDR:	equ	112h
CSD_1SW33_IntCtrl_1_ADDR:	equ	113h
CSD_1SW33_IntEn_ADDR:	equ	11h
CSD_1SW33_MASK:	equ	80h
CSD_1SW33_MUXBusCtrl_ADDR:	equ	1ech
; CSD_1SW33_Data access macros
;   GetCSD_1SW33_Data macro, return in a
macro GetCSD_1SW33_Data
	mov		a,[Port_4_Data_SHADE]
	and		a, 80h
endm
;   SetCSD_1SW33_Data macro
macro SetCSD_1SW33_Data
	or		[Port_4_Data_SHADE], 80h
	mov		reg[Port_4_Data], [Port_4_Data_SHADE]
endm
;   SetCSD_1SW33_Data macro
macro ClearCSD_1SW33_Data
	and		[Port_4_Data_SHADE], ~80h
	mov		reg[Port_4_Data], [Port_4_Data_SHADE]
endm

; CSD_1SW5 address and mask equates
CSD_1SW5_Data_ADDR:	equ	14h
CSD_1SW5_DriveMode_0_ADDR:	equ	114h
CSD_1SW5_DriveMode_1_ADDR:	equ	115h
CSD_1SW5_DriveMode_2_ADDR:	equ	17h
CSD_1SW5_GlobalSelect_ADDR:	equ	16h
CSD_1SW5_IntCtrl_0_ADDR:	equ	116h
CSD_1SW5_IntCtrl_1_ADDR:	equ	117h
CSD_1SW5_IntEn_ADDR:	equ	15h
CSD_1SW5_MASK:	equ	1h
CSD_1SW5_MUXBusCtrl_ADDR:	equ	1edh
; CSD_1SW5_Data access macros
;   GetCSD_1SW5_Data macro, return in a
macro GetCSD_1SW5_Data
	mov		a,[Port_5_Data_SHADE]
	and		a, 1h
endm
;   SetCSD_1SW5_Data macro
macro SetCSD_1SW5_Data
	or		[Port_5_Data_SHADE], 1h
	mov		reg[Port_5_Data], [Port_5_Data_SHADE]
endm
;   SetCSD_1SW5_Data macro
macro ClearCSD_1SW5_Data
	and		[Port_5_Data_SHADE], ~1h
	mov		reg[Port_5_Data], [Port_5_Data_SHADE]
endm

; CSD_1SW19 address and mask equates
CSD_1SW19_Data_ADDR:	equ	14h
CSD_1SW19_DriveMode_0_ADDR:	equ	114h
CSD_1SW19_DriveMode_1_ADDR:	equ	115h
CSD_1SW19_DriveMode_2_ADDR:	equ	17h
CSD_1SW19_GlobalSelect_ADDR:	equ	16h
CSD_1SW19_IntCtrl_0_ADDR:	equ	116h
CSD_1SW19_IntCtrl_1_ADDR:	equ	117h
CSD_1SW19_IntEn_ADDR:	equ	15h
CSD_1SW19_MASK:	equ	2h
CSD_1SW19_MUXBusCtrl_ADDR:	equ	1edh
; CSD_1SW19_Data access macros
;   GetCSD_1SW19_Data macro, return in a
macro GetCSD_1SW19_Data
	mov		a,[Port_5_Data_SHADE]
	and		a, 2h
endm
;   SetCSD_1SW19_Data macro
macro SetCSD_1SW19_Data
	or		[Port_5_Data_SHADE], 2h
	mov		reg[Port_5_Data], [Port_5_Data_SHADE]
endm
;   SetCSD_1SW19_Data macro
macro ClearCSD_1SW19_Data
	and		[Port_5_Data_SHADE], ~2h
	mov		reg[Port_5_Data], [Port_5_Data_SHADE]
endm

; CSD_1SW11 address and mask equates
CSD_1SW11_Data_ADDR:	equ	14h
CSD_1SW11_DriveMode_0_ADDR:	equ	114h
CSD_1SW11_DriveMode_1_ADDR:	equ	115h
CSD_1SW11_DriveMode_2_ADDR:	equ	17h
CSD_1SW11_GlobalSelect_ADDR:	equ	16h
CSD_1SW11_IntCtrl_0_ADDR:	equ	116h
CSD_1SW11_IntCtrl_1_ADDR:	equ	117h
CSD_1SW11_IntEn_ADDR:	equ	15h
CSD_1SW11_MASK:	equ	4h
CSD_1SW11_MUXBusCtrl_ADDR:	equ	1edh
; CSD_1SW11_Data access macros
;   GetCSD_1SW11_Data macro, return in a
macro GetCSD_1SW11_Data
	mov		a,[Port_5_Data_SHADE]
	and		a, 4h
endm
;   SetCSD_1SW11_Data macro
macro SetCSD_1SW11_Data
	or		[Port_5_Data_SHADE], 4h
	mov		reg[Port_5_Data], [Port_5_Data_SHADE]
endm
;   SetCSD_1SW11_Data macro
macro ClearCSD_1SW11_Data
	and		[Port_5_Data_SHADE], ~4h
	mov		reg[Port_5_Data], [Port_5_Data_SHADE]
endm

; CSD_1SW23 address and mask equates
CSD_1SW23_Data_ADDR:	equ	14h
CSD_1SW23_DriveMode_0_ADDR:	equ	114h
CSD_1SW23_DriveMode_1_ADDR:	equ	115h
CSD_1SW23_DriveMode_2_ADDR:	equ	17h
CSD_1SW23_GlobalSelect_ADDR:	equ	16h
CSD_1SW23_IntCtrl_0_ADDR:	equ	116h
CSD_1SW23_IntCtrl_1_ADDR:	equ	117h
CSD_1SW23_IntEn_ADDR:	equ	15h
CSD_1SW23_MASK:	equ	8h
CSD_1SW23_MUXBusCtrl_ADDR:	equ	1edh
; CSD_1SW23_Data access macros
;   GetCSD_1SW23_Data macro, return in a
macro GetCSD_1SW23_Data
	mov		a,[Port_5_Data_SHADE]
	and		a, 8h
endm
;   SetCSD_1SW23_Data macro
macro SetCSD_1SW23_Data
	or		[Port_5_Data_SHADE], 8h
	mov		reg[Port_5_Data], [Port_5_Data_SHADE]
endm
;   SetCSD_1SW23_Data macro
macro ClearCSD_1SW23_Data
	and		[Port_5_Data_SHADE], ~8h
	mov		reg[Port_5_Data], [Port_5_Data_SHADE]
endm

; CSD_1SW1 address and mask equates
CSD_1SW1_Data_ADDR:	equ	14h
CSD_1SW1_DriveMode_0_ADDR:	equ	114h
CSD_1SW1_DriveMode_1_ADDR:	equ	115h
CSD_1SW1_DriveMode_2_ADDR:	equ	17h
CSD_1SW1_GlobalSelect_ADDR:	equ	16h
CSD_1SW1_IntCtrl_0_ADDR:	equ	116h
CSD_1SW1_IntCtrl_1_ADDR:	equ	117h
CSD_1SW1_IntEn_ADDR:	equ	15h
CSD_1SW1_MASK:	equ	10h
CSD_1SW1_MUXBusCtrl_ADDR:	equ	1edh
; CSD_1SW1_Data access macros
;   GetCSD_1SW1_Data macro, return in a
macro GetCSD_1SW1_Data
	mov		a,[Port_5_Data_SHADE]
	and		a, 10h
endm
;   SetCSD_1SW1_Data macro
macro SetCSD_1SW1_Data
	or		[Port_5_Data_SHADE], 10h
	mov		reg[Port_5_Data], [Port_5_Data_SHADE]
endm
;   SetCSD_1SW1_Data macro
macro ClearCSD_1SW1_Data
	and		[Port_5_Data_SHADE], ~10h
	mov		reg[Port_5_Data], [Port_5_Data_SHADE]
endm

; CSD_1SW29 address and mask equates
CSD_1SW29_Data_ADDR:	equ	14h
CSD_1SW29_DriveMode_0_ADDR:	equ	114h
CSD_1SW29_DriveMode_1_ADDR:	equ	115h
CSD_1SW29_DriveMode_2_ADDR:	equ	17h
CSD_1SW29_GlobalSelect_ADDR:	equ	16h
CSD_1SW29_IntCtrl_0_ADDR:	equ	116h
CSD_1SW29_IntCtrl_1_ADDR:	equ	117h
CSD_1SW29_IntEn_ADDR:	equ	15h
CSD_1SW29_MASK:	equ	20h
CSD_1SW29_MUXBusCtrl_ADDR:	equ	1edh
; CSD_1SW29_Data access macros
;   GetCSD_1SW29_Data macro, return in a
macro GetCSD_1SW29_Data
	mov		a,[Port_5_Data_SHADE]
	and		a, 20h
endm
;   SetCSD_1SW29_Data macro
macro SetCSD_1SW29_Data
	or		[Port_5_Data_SHADE], 20h
	mov		reg[Port_5_Data], [Port_5_Data_SHADE]
endm
;   SetCSD_1SW29_Data macro
macro ClearCSD_1SW29_Data
	and		[Port_5_Data_SHADE], ~20h
	mov		reg[Port_5_Data], [Port_5_Data_SHADE]
endm

; CSD_1SW12 address and mask equates
CSD_1SW12_Data_ADDR:	equ	14h
CSD_1SW12_DriveMode_0_ADDR:	equ	114h
CSD_1SW12_DriveMode_1_ADDR:	equ	115h
CSD_1SW12_DriveMode_2_ADDR:	equ	17h
CSD_1SW12_GlobalSelect_ADDR:	equ	16h
CSD_1SW12_IntCtrl_0_ADDR:	equ	116h
CSD_1SW12_IntCtrl_1_ADDR:	equ	117h
CSD_1SW12_IntEn_ADDR:	equ	15h
CSD_1SW12_MASK:	equ	40h
CSD_1SW12_MUXBusCtrl_ADDR:	equ	1edh
; CSD_1SW12_Data access macros
;   GetCSD_1SW12_Data macro, return in a
macro GetCSD_1SW12_Data
	mov		a,[Port_5_Data_SHADE]
	and		a, 40h
endm
;   SetCSD_1SW12_Data macro
macro SetCSD_1SW12_Data
	or		[Port_5_Data_SHADE], 40h
	mov		reg[Port_5_Data], [Port_5_Data_SHADE]
endm
;   SetCSD_1SW12_Data macro
macro ClearCSD_1SW12_Data
	and		[Port_5_Data_SHADE], ~40h
	mov		reg[Port_5_Data], [Port_5_Data_SHADE]
endm

; CSD_1SW30 address and mask equates
CSD_1SW30_Data_ADDR:	equ	14h
CSD_1SW30_DriveMode_0_ADDR:	equ	114h
CSD_1SW30_DriveMode_1_ADDR:	equ	115h
CSD_1SW30_DriveMode_2_ADDR:	equ	17h
CSD_1SW30_GlobalSelect_ADDR:	equ	16h
CSD_1SW30_IntCtrl_0_ADDR:	equ	116h
CSD_1SW30_IntCtrl_1_ADDR:	equ	117h
CSD_1SW30_IntEn_ADDR:	equ	15h
CSD_1SW30_MASK:	equ	80h
CSD_1SW30_MUXBusCtrl_ADDR:	equ	1edh
; CSD_1SW30_Data access macros
;   GetCSD_1SW30_Data macro, return in a
macro GetCSD_1SW30_Data
	mov		a,[Port_5_Data_SHADE]
	and		a, 80h
endm
;   SetCSD_1SW30_Data macro
macro SetCSD_1SW30_Data
	or		[Port_5_Data_SHADE], 80h
	mov		reg[Port_5_Data], [Port_5_Data_SHADE]
endm
;   SetCSD_1SW30_Data macro
macro ClearCSD_1SW30_Data
	and		[Port_5_Data_SHADE], ~80h
	mov		reg[Port_5_Data], [Port_5_Data_SHADE]
endm