psocgpioint.inc

cypresscy74294ic键盘和鼠标原码

; Generated by PSoC Designer ver 4.4  b1884 : 14 Jan, 2007
;
; CSD_1SW16 address and mask equates
CSD_1SW16_Data_ADDR:	equ	0h
CSD_1SW16_DriveMode_0_ADDR:	equ	100h
CSD_1SW16_DriveMode_1_ADDR:	equ	101h
CSD_1SW16_DriveMode_2_ADDR:	equ	3h
CSD_1SW16_GlobalSelect_ADDR:	equ	2h
CSD_1SW16_IntCtrl_0_ADDR:	equ	102h
CSD_1SW16_IntCtrl_1_ADDR:	equ	103h
CSD_1SW16_IntEn_ADDR:	equ	1h
CSD_1SW16_MASK:	equ	1h
CSD_1SW16_MUXBusCtrl_ADDR:	equ	1d8h
; CSD_1SW16_Data access macros
;   GetCSD_1SW16_Data macro, return in a
macro GetCSD_1SW16_Data
	mov		a,[Port_0_Data_SHADE]
	and		a, 1h
endm
;   SetCSD_1SW16_Data macro
macro SetCSD_1SW16_Data
	or		[Port_0_Data_SHADE], 1h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm
;   SetCSD_1SW16_Data macro
macro ClearCSD_1SW16_Data
	and		[Port_0_Data_SHADE], ~1h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm

; CSD_1SW34 address and mask equates
CSD_1SW34_Data_ADDR:	equ	0h
CSD_1SW34_DriveMode_0_ADDR:	equ	100h
CSD_1SW34_DriveMode_1_ADDR:	equ	101h
CSD_1SW34_DriveMode_2_ADDR:	equ	3h
CSD_1SW34_GlobalSelect_ADDR:	equ	2h
CSD_1SW34_IntCtrl_0_ADDR:	equ	102h
CSD_1SW34_IntCtrl_1_ADDR:	equ	103h
CSD_1SW34_IntEn_ADDR:	equ	1h
CSD_1SW34_MASK:	equ	2h
CSD_1SW34_MUXBusCtrl_ADDR:	equ	1d8h
; CSD_1SW34_Data access macros
;   GetCSD_1SW34_Data macro, return in a
macro GetCSD_1SW34_Data
	mov		a,[Port_0_Data_SHADE]
	and		a, 2h
endm
;   SetCSD_1SW34_Data macro
macro SetCSD_1SW34_Data
	or		[Port_0_Data_SHADE], 2h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm
;   SetCSD_1SW34_Data macro
macro ClearCSD_1SW34_Data
	and		[Port_0_Data_SHADE], ~2h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm

; CSD_1SW4 address and mask equates
CSD_1SW4_Data_ADDR:	equ	0h
CSD_1SW4_DriveMode_0_ADDR:	equ	100h
CSD_1SW4_DriveMode_1_ADDR:	equ	101h
CSD_1SW4_DriveMode_2_ADDR:	equ	3h
CSD_1SW4_GlobalSelect_ADDR:	equ	2h
CSD_1SW4_IntCtrl_0_ADDR:	equ	102h
CSD_1SW4_IntCtrl_1_ADDR:	equ	103h
CSD_1SW4_IntEn_ADDR:	equ	1h
CSD_1SW4_MASK:	equ	4h
CSD_1SW4_MUXBusCtrl_ADDR:	equ	1d8h
; CSD_1SW4_Data access macros
;   GetCSD_1SW4_Data macro, return in a
macro GetCSD_1SW4_Data
	mov		a,[Port_0_Data_SHADE]
	and		a, 4h
endm
;   SetCSD_1SW4_Data macro
macro SetCSD_1SW4_Data
	or		[Port_0_Data_SHADE], 4h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm
;   SetCSD_1SW4_Data macro
macro ClearCSD_1SW4_Data
	and		[Port_0_Data_SHADE], ~4h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm

; CSD_1SW22 address and mask equates
CSD_1SW22_Data_ADDR:	equ	0h
CSD_1SW22_DriveMode_0_ADDR:	equ	100h
CSD_1SW22_DriveMode_1_ADDR:	equ	101h
CSD_1SW22_DriveMode_2_ADDR:	equ	3h
CSD_1SW22_GlobalSelect_ADDR:	equ	2h
CSD_1SW22_IntCtrl_0_ADDR:	equ	102h
CSD_1SW22_IntCtrl_1_ADDR:	equ	103h
CSD_1SW22_IntEn_ADDR:	equ	1h
CSD_1SW22_MASK:	equ	8h
CSD_1SW22_MUXBusCtrl_ADDR:	equ	1d8h
; CSD_1SW22_Data access macros
;   GetCSD_1SW22_Data macro, return in a
macro GetCSD_1SW22_Data
	mov		a,[Port_0_Data_SHADE]
	and		a, 8h
endm
;   SetCSD_1SW22_Data macro
macro SetCSD_1SW22_Data
	or		[Port_0_Data_SHADE], 8h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm
;   SetCSD_1SW22_Data macro
macro ClearCSD_1SW22_Data
	and		[Port_0_Data_SHADE], ~8h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm

; CSD_1SW10 address and mask equates
CSD_1SW10_Data_ADDR:	equ	0h
CSD_1SW10_DriveMode_0_ADDR:	equ	100h
CSD_1SW10_DriveMode_1_ADDR:	equ	101h
CSD_1SW10_DriveMode_2_ADDR:	equ	3h
CSD_1SW10_GlobalSelect_ADDR:	equ	2h
CSD_1SW10_IntCtrl_0_ADDR:	equ	102h
CSD_1SW10_IntCtrl_1_ADDR:	equ	103h
CSD_1SW10_IntEn_ADDR:	equ	1h
CSD_1SW10_MASK:	equ	10h
CSD_1SW10_MUXBusCtrl_ADDR:	equ	1d8h
; CSD_1SW10_Data access macros
;   GetCSD_1SW10_Data macro, return in a
macro GetCSD_1SW10_Data
	mov		a,[Port_0_Data_SHADE]
	and		a, 10h
endm
;   SetCSD_1SW10_Data macro
macro SetCSD_1SW10_Data
	or		[Port_0_Data_SHADE], 10h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm
;   SetCSD_1SW10_Data macro
macro ClearCSD_1SW10_Data
	and		[Port_0_Data_SHADE], ~10h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm

; CSD_1SW28 address and mask equates
CSD_1SW28_Data_ADDR:	equ	0h
CSD_1SW28_DriveMode_0_ADDR:	equ	100h
CSD_1SW28_DriveMode_1_ADDR:	equ	101h
CSD_1SW28_DriveMode_2_ADDR:	equ	3h
CSD_1SW28_GlobalSelect_ADDR:	equ	2h
CSD_1SW28_IntCtrl_0_ADDR:	equ	102h
CSD_1SW28_IntCtrl_1_ADDR:	equ	103h
CSD_1SW28_IntEn_ADDR:	equ	1h
CSD_1SW28_MASK:	equ	20h
CSD_1SW28_MUXBusCtrl_ADDR:	equ	1d8h
; CSD_1SW28_Data access macros
;   GetCSD_1SW28_Data macro, return in a
macro GetCSD_1SW28_Data
	mov		a,[Port_0_Data_SHADE]
	and		a, 20h
endm
;   SetCSD_1SW28_Data macro
macro SetCSD_1SW28_Data
	or		[Port_0_Data_SHADE], 20h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm
;   SetCSD_1SW28_Data macro
macro ClearCSD_1SW28_Data
	and		[Port_0_Data_SHADE], ~20h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm

; CSD_1SW17 address and mask equates
CSD_1SW17_Data_ADDR:	equ	0h
CSD_1SW17_DriveMode_0_ADDR:	equ	100h
CSD_1SW17_DriveMode_1_ADDR:	equ	101h
CSD_1SW17_DriveMode_2_ADDR:	equ	3h
CSD_1SW17_GlobalSelect_ADDR:	equ	2h
CSD_1SW17_IntCtrl_0_ADDR:	equ	102h
CSD_1SW17_IntCtrl_1_ADDR:	equ	103h
CSD_1SW17_IntEn_ADDR:	equ	1h
CSD_1SW17_MASK:	equ	40h
CSD_1SW17_MUXBusCtrl_ADDR:	equ	1d8h
; CSD_1SW17_Data access macros
;   GetCSD_1SW17_Data macro, return in a
macro GetCSD_1SW17_Data
	mov		a,[Port_0_Data_SHADE]
	and		a, 40h
endm
;   SetCSD_1SW17_Data macro
macro SetCSD_1SW17_Data
	or		[Port_0_Data_SHADE], 40h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm
;   SetCSD_1SW17_Data macro
macro ClearCSD_1SW17_Data
	and		[Port_0_Data_SHADE], ~40h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm

; CSD_1Capacitor address and mask equates
CSD_1Capacitor_Data_ADDR:	equ	0h
CSD_1Capacitor_DriveMode_0_ADDR:	equ	100h
CSD_1Capacitor_DriveMode_1_ADDR:	equ	101h
CSD_1Capacitor_DriveMode_2_ADDR:	equ	3h
CSD_1Capacitor_GlobalSelect_ADDR:	equ	2h
CSD_1Capacitor_IntCtrl_0_ADDR:	equ	102h
CSD_1Capacitor_IntCtrl_1_ADDR:	equ	103h
CSD_1Capacitor_IntEn_ADDR:	equ	1h
CSD_1Capacitor_MASK:	equ	80h
CSD_1Capacitor_MUXBusCtrl_ADDR:	equ	1d8h
; CSD_1Capacitor_Data access macros
;   GetCSD_1Capacitor_Data macro, return in a
macro GetCSD_1Capacitor_Data
	mov		a,[Port_0_Data_SHADE]
	and		a, 80h
endm
;   SetCSD_1Capacitor_Data macro
macro SetCSD_1Capacitor_Data
	or		[Port_0_Data_SHADE], 80h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm
;   SetCSD_1Capacitor_Data macro
macro ClearCSD_1Capacitor_Data
	and		[Port_0_Data_SHADE], ~80h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm

; LED_ShiftCAPPin address and mask equates
LED_ShiftCAPPin_Data_ADDR:	equ	4h
LED_ShiftCAPPin_DriveMode_0_ADDR:	equ	104h
LED_ShiftCAPPin_DriveMode_1_ADDR:	equ	105h
LED_ShiftCAPPin_DriveMode_2_ADDR:	equ	7h
LED_ShiftCAPPin_GlobalSelect_ADDR:	equ	6h
LED_ShiftCAPPin_IntCtrl_0_ADDR:	equ	106h
LED_ShiftCAPPin_IntCtrl_1_ADDR:	equ	107h
LED_ShiftCAPPin_IntEn_ADDR:	equ	5h
LED_ShiftCAPPin_MASK:	equ	10h
LED_ShiftCAPPin_MUXBusCtrl_ADDR:	equ	1d9h
; LED_ShiftCAPPin_Data access macros
;   GetLED_ShiftCAPPin_Data macro, return in a
macro GetLED_ShiftCAPPin_Data
	mov		a,[Port_1_Data_SHADE]
	and		a, 10h
endm
;   SetLED_ShiftCAPPin_Data macro
macro SetLED_ShiftCAPPin_Data
	or		[Port_1_Data_SHADE], 10h
	mov		reg[Port_1_Data], [Port_1_Data_SHADE]
endm
;   SetLED_ShiftCAPPin_Data macro
macro ClearLED_ShiftCAPPin_Data
	and		[Port_1_Data_SHADE], ~10h
	mov		reg[Port_1_Data], [Port_1_Data_SHADE]
endm

; CSD_1Resistor address and mask equates
CSD_1Resistor_Data_ADDR:	equ	4h
CSD_1Resistor_DriveMode_0_ADDR:	equ	104h
CSD_1Resistor_DriveMode_1_ADDR:	equ	105h
CSD_1Resistor_DriveMode_2_ADDR:	equ	7h
CSD_1Resistor_GlobalSelect_ADDR:	equ	6h
CSD_1Resistor_IntCtrl_0_ADDR:	equ	106h
CSD_1Resistor_IntCtrl_1_ADDR:	equ	107h
CSD_1Resistor_IntEn_ADDR:	equ	5h
CSD_1Resistor_MASK:	equ	20h
CSD_1Resistor_MUXBusCtrl_ADDR:	equ	1d9h
; CSD_1Resistor_Data access macros
;   GetCSD_1Resistor_Data macro, return in a
macro GetCSD_1Resistor_Data
	mov		a,[Port_1_Data_SHADE]
	and		a, 20h
endm
;   SetCSD_1Resistor_Data macro
macro SetCSD_1Resistor_Data
	or		[Port_1_Data_SHADE], 20h
	mov		reg[Port_1_Data], [Port_1_Data_SHADE]
endm
;   SetCSD_1Resistor_Data macro
macro ClearCSD_1Resistor_Data
	and		[Port_1_Data_SHADE], ~20h
	mov		reg[Port_1_Data], [Port_1_Data_SHADE]
endm

; BeepPin address and mask equates
BeepPin_Data_ADDR:	equ	4h
BeepPin_DriveMode_0_ADDR:	equ	104h
BeepPin_DriveMode_1_ADDR:	equ	105h
BeepPin_DriveMode_2_ADDR:	equ	7h
BeepPin_GlobalSelect_ADDR:	equ	6h
BeepPin_IntCtrl_0_ADDR:	equ	106h
BeepPin_IntCtrl_1_ADDR:	equ	107h
BeepPin_IntEn_ADDR:	equ	5h
BeepPin_MASK:	equ	40h
BeepPin_MUXBusCtrl_ADDR:	equ	1d9h
; BeepPin_Data access macros
;   GetBeepPin_Data macro, return in a
macro GetBeepPin_Data
	mov		a,[Port_1_Data_SHADE]
	and		a, 40h
endm
;   SetBeepPin_Data macro
macro SetBeepPin_Data
	or		[Port_1_Data_SHADE], 40h
	mov		reg[Port_1_Data], [Port_1_Data_SHADE]
endm
;   SetBeepPin_Data macro
macro ClearBeepPin_Data
	and		[Port_1_Data_SHADE], ~40h
	mov		reg[Port_1_Data], [Port_1_Data_SHADE]
endm

; CSD_1SW35 address and mask equates
CSD_1SW35_Data_ADDR:	equ	4h
CSD_1SW35_DriveMode_0_ADDR:	equ	104h
CSD_1SW35_DriveMode_1_ADDR:	equ	105h
CSD_1SW35_DriveMode_2_ADDR:	equ	7h
CSD_1SW35_GlobalSelect_ADDR:	equ	6h
CSD_1SW35_IntCtrl_0_ADDR:	equ	106h
CSD_1SW35_IntCtrl_1_ADDR:	equ	107h
CSD_1SW35_IntEn_ADDR:	equ	5h
CSD_1SW35_MASK:	equ	80h
CSD_1SW35_MUXBusCtrl_ADDR:	equ	1d9h
; CSD_1SW35_Data access macros
;   GetCSD_1SW35_Data macro, return in a
macro GetCSD_1SW35_Data
	mov		a,[Port_1_Data_SHADE]
	and		a, 80h
endm
;   SetCSD_1SW35_Data macro
macro SetCSD_1SW35_Data
	or		[Port_1_Data_SHADE], 80h
	mov		reg[Port_1_Data], [Port_1_Data_SHADE]
endm
;   SetCSD_1SW35_Data macro
macro ClearCSD_1SW35_Data
	and		[Port_1_Data_SHADE], ~80h
	mov		reg[Port_1_Data], [Port_1_Data_SHADE]
endm

; CSD_1SW3 address and mask equates
CSD_1SW3_Data_ADDR:	equ	8h
CSD_1SW3_DriveMode_0_ADDR:	equ	108h
CSD_1SW3_DriveMode_1_ADDR:	equ	109h
CSD_1SW3_DriveMode_2_ADDR:	equ	bh
CSD_1SW3_GlobalSelect_ADDR:	equ	ah
CSD_1SW3_IntCtrl_0_ADDR:	equ	10ah
CSD_1SW3_IntCtrl_1_ADDR:	equ	10bh
CSD_1SW3_IntEn_ADDR:	equ	9h
CSD_1SW3_MASK:	equ	10h
CSD_1SW3_MUXBusCtrl_ADDR:	equ	1dah
; CSD_1SW3_Data access macros
;   GetCSD_1SW3_Data macro, return in a
macro GetCSD_1SW3_Data
	mov		a,[Port_2_Data_SHADE]
	and		a, 10h
endm
;   SetCSD_1SW3_Data macro
macro SetCSD_1SW3_Data
	or		[Port_2_Data_SHADE], 10h
	mov		reg[Port_2_Data], [Port_2_Data_SHADE]
endm
;   SetCSD_1SW3_Data macro
macro ClearCSD_1SW3_Data
	and		[Port_2_Data_SHADE], ~10h
	mov		reg[Port_2_Data], [Port_2_Data_SHADE]
endm

; CSD_1SW21 address and mask equates
CSD_1SW21_Data_ADDR:	equ	8h
CSD_1SW21_DriveMode_0_ADDR:	equ	108h
CSD_1SW21_DriveMode_1_ADDR:	equ	109h
CSD_1SW21_DriveMode_2_ADDR:	equ	bh
CSD_1SW21_GlobalSelect_ADDR:	equ	ah
CSD_1SW21_IntCtrl_0_ADDR:	equ	10ah
CSD_1SW21_IntCtrl_1_ADDR:	equ	10bh
CSD_1SW21_IntEn_ADDR:	equ	9h