📄 unisen_kb.lst
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(0351) .AccessStruct: ; Entry point for first block
(0352) ;
(0353) ; Assert: pXIData in [A,X] points to the beginning of an XIData struct.
(0354) ;
00C7: 62 E3 00 MOV REG[227],0 (0355) M8C_ClearWDT ; Clear the watchdog for long inits
00CA: 08 PUSH A (0356) push A
00CB: 28 ROMX (0357) romx ; MSB of RAM addr (CPU.A <- *pXIData)
00CC: 60 D5 MOV REG[213],A (0358) mov reg[MVW_PP], A ; for use with MVI write operations
00CE: 74 INC A (0359) inc A ; End of Struct List? (MSB==0xFF?)
00CF: A0 4B JZ 0x011B (0360) jz .C_RTE_WrapUp ; Yes, C runtime environment complete
00D1: 18 POP A (0361) pop A ; restore pXIData to [A,X]
00D2: 75 INC X (0362) inc X ; pXIData++
00D3: 09 00 ADC A,0 (0363) adc A, 0
00D5: 08 PUSH A (0364) push A
00D6: 28 ROMX (0365) romx ; LSB of RAM addr (CPU.A <- *pXIData)
00D7: 53 D5 MOV [__r0],A (0366) mov [__r0], A ; RAM Addr now in [reg[MVW_PP],[__r0]]
00D9: 18 POP A (0367) pop A ; restore pXIData to [A,X]
00DA: 75 INC X (0368) inc X ; pXIData++ (point to size)
00DB: 09 00 ADC A,0 (0369) adc A, 0
00DD: 08 PUSH A (0370) push A
00DE: 28 ROMX (0371) romx ; Get the size (CPU.A <- *pXIData)
00DF: A0 1C JZ 0x00FC (0372) jz .ClearRAMBlockToZero ; If Size==0, then go clear RAM
00E1: 53 D4 MOV [__r1],A (0373) mov [__r1], A ; else downcount in __r1
00E3: 18 POP A (0374) pop A ; restore pXIData to [A,X]
(0375)
(0376) .CopyNextByteLoop:
(0377) ; For each byte in the structure's array member, copy from flash to RAM.
(0378) ; Assert: pXIData in [A,X] points to previous byte of flash source;
(0379) ; [reg[MVW_PP],[__r0]] points to next RAM destination;
(0380) ; __r1 holds a non-zero count of the number of bytes remaining.
(0381) ;
00E4: 75 INC X (0382) inc X ; pXIData++ (point to next data byte)
00E5: 09 00 ADC A,0 (0383) adc A, 0
00E7: 08 PUSH A (0384) push A
00E8: 28 ROMX (0385) romx ; Get the data value (CPU.A <- *pXIData)
00E9: 3F D5 MVI [__r0],A (0386) mvi [__r0], A ; Transfer the data to RAM
00EB: 47 D5 FF TST [213],255 (0387) tst [__r0], 0xff ; Check for page crossing
00EE: B0 06 JNZ 0x00F5 (0388) jnz .CopyLoopTail ; No crossing, keep going
00F0: 5D D5 MOV A,REG[213] (0389) mov A, reg[ MVW_PP] ; If crossing, bump MVW page reg
00F2: 74 INC A (0390) inc A
00F3: 60 D5 MOV REG[213],A (0391) mov reg[ MVW_PP], A
(0392) .CopyLoopTail:
00F5: 18 POP A (0393) pop A ; restore pXIData to [A,X]
00F6: 7A D4 DEC [__r1] (0394) dec [__r1] ; End of this array in flash?
00F8: BF EB JNZ 0x00E4 (0395) jnz .CopyNextByteLoop ; No, more bytes to copy
00FA: 8F C9 JMP 0x00C4 (0396) jmp .AccessNextStructLoop ; Yes, initialize another RAM block
(0397)
(0398) .ClearRAMBlockToZero:
00FC: 18 POP A (0399) pop A ; restore pXIData to [A,X]
00FD: 75 INC X (0400) inc X ; pXIData++ (point to next data byte)
00FE: 09 00 ADC A,0 (0401) adc A, 0
0100: 08 PUSH A (0402) push A
0101: 28 ROMX (0403) romx ; Get the run length (CPU.A <- *pXIData)
0102: 53 D4 MOV [__r1],A (0404) mov [__r1], A ; Initialize downcounter
0104: 50 00 MOV A,0 (0405) mov A, 0 ; Initialize source data
(0406)
(0407) .ClearRAMBlockLoop:
(0408) ; Assert: [reg[MVW_PP],[__r0]] points to next RAM destination and
(0409) ; __r1 holds a non-zero count of the number of bytes remaining.
(0410) ;
0106: 3F D5 MVI [__r0],A (0411) mvi [__r0], A ; Clear a byte
0108: 47 D5 FF TST [213],255 (0412) tst [__r0], 0xff ; Check for page crossing
010B: B0 08 JNZ 0x0114 (0413) jnz .ClearLoopTail ; No crossing, keep going
010D: 5D D5 MOV A,REG[213] (0414) mov A, reg[ MVW_PP] ; If crossing, bump MVW page reg
010F: 74 INC A (0415) inc A
0110: 60 D5 MOV REG[213],A (0416) mov reg[ MVW_PP], A
0112: 50 00 MOV A,0 (0417) mov A, 0 ; Restore the zero used for clearing
(0418) .ClearLoopTail:
0114: 7A D4 DEC [__r1] (0419) dec [__r1] ; Was this the last byte?
0116: BF EF JNZ 0x0106 (0420) jnz .ClearRAMBlockLoop ; No, continue
0118: 18 POP A (0421) pop A ; Yes, restore pXIData to [A,X] and
0119: 8F AA JMP 0x00C4 (0422) jmp .AccessNextStructLoop ; initialize another RAM block
(0423)
(0424) .C_RTE_WrapUp:
011B: 18 POP A (0425) pop A ; balance stack
(0426)
(0427) ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
(0428)
(0429) C_RTE_Done:
(0430)
(0431) ENDIF ; C_LANGUAGE_SUPPORT
(0432)
(0433)
(0434) ;-------------------------------
(0435) ; Set Power-On Reset (POR) Level
(0436) ;-------------------------------
011C: 71 10 OR F,16 (0437) M8C_SetBank1
(0438)
(0439) IF (POWER_SETTING & POWER_SET_3V3) ; 3.3V Operation?
(0440) or reg[VLT_CR], VLT_CR_POR_LOW ; Yes, change to midpoint trip
(0441) ELSE ; 5V Operation
(0442) IF ( CPU_CLOCK_JUST ^ OSC_CR0_CPU_24MHz ) ; As fast as 24MHz?
011E: 43 E3 00 OR REG[227],0 (0443) or reg[VLT_CR], VLT_CR_POR_LOW ; No, change to midpoint trip
(0444) ELSE ; 24HMz ;
(0445) or reg[VLT_CR], VLT_CR_POR_HIGH ; Yes, switch to highest setting
(0446) ENDIF ; 24MHz
(0447) ENDIF ; 3.3V Operation
(0448)
0121: 70 EF AND F,239 (0449) M8C_SetBank0
(0450)
(0451) ;----------------------------
(0452) ; Wrap up and invoke "main"
(0453) ;----------------------------
(0454)
(0455) ; Disable the Sleep interrupt that was used for timing above. In fact,
(0456) ; no interrupts should be enabled now, so may as well clear the register.
(0457) ;
0123: 62 E0 00 MOV REG[224],0 (0458) mov reg[INT_MSK0],0
(0459)
(0460) ; Everything has started OK. Now select requested CPU & sleep frequency.
(0461) ;
0126: 71 10 OR F,16 (0462) M8C_SetBank1
0128: 62 E0 02 MOV REG[224],2 (0463) mov reg[OSC_CR0],(SLEEP_TIMER_JUST | CPU_CLOCK_JUST)
012B: 70 EF AND F,239 (0464) M8C_SetBank0
(0465)
(0466) ; Global Interrupt are NOT enabled, this should be done in main().
(0467) ; LVD is set but will not occur unless Global Interrupts are enabled.
(0468) ; Global Interrupts should be enabled as soon as possible in main().
(0469) ;
012D: 62 E2 00 MOV REG[226],0 (0470) mov reg[INT_VC],0 ; Clear any pending interrupts which may
(0471) ; have been set during the boot process.
(0472) IF ENABLE_LJMP_TO_MAIN
(0473) ljmp _main ; goto main (no return)
(0474) ELSE
0130: 7C 1E 71 LCALL _main (0475) lcall _main ; call main
(0476) .Exit:
0133: 8F FF JMP 0x0133 (0477) jmp .Exit ; Wait here after return till power-off or reset
(0478) ENDIF
(0479)
(0480) ;---------------------------------
(0481) ; Library Access to Global Parms
(0482) ;---------------------------------
(0483) ;
(0484) bGetPowerSetting:
(0485) _bGetPowerSetting:
(0486) ; Returns value of POWER_SETTING in the A register.
(0487) ; No inputs. No Side Effects.
(0488) ;
0135: 50 10 MOV A,16 (0489) mov A, POWER_SETTING ; Supply voltage and internal main osc
0137: 7F RET (0490) ret
0138: 30 HALT
0139: 30 HALT
013A: 30 HALT
013B: 30 HALT
013C: 30 HALT
013D: 30 HALT
013E: 30 HALT
013F: 30 HALT
0140: 30 HALT
0141: 30 HALT
0142: 30 HALT
0143: 30 HALT
0144: 30 HALT
0145: 30 HALT
0146: 30 HALT
0147: 30 HALT
0148: 30 HALT
0149: 30 HALT
014A: 30 HALT
014B: 30 HALT
014C: 30 HALT
014D: 30 HALT
014E: 30 HALT
014F: 30 HALT
0150: 30 HALT
0151: 30 HALT
0152: 30 HALT
0153: 30 HALT
0154: 30 HALT
0155: 30 HALT
0156: 30 HALT
0157: 30 HALT
0158: 30 HALT
0159: 30 HALT
015A: 30 HALT
015B: 30 HALT
015C: 30 HALT
015D: 30 HALT
015E: 30 HALT
015F: 30 HALT
0160: 30 HALT
0161: 30 HALT
0162: 30 HALT
0163: 30 HALT
0164: 30 HALT
0165: 30 HALT
0166: 30 HALT
0167: 30 HALT
0168: 30 HALT
0169: 30 HALT
016A: 30 HALT
016B: 30 HALT
016C: 30 HALT
016D: 30 HALT
016E: 30 HALT
016F: 30 HALT
0170: 30 HALT
0171: 30 HALT
0172: 30 HALT
0173: 30 HALT
0174: 30 HALT
0175: 30 HALT
0176: 30 HALT
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