📄 unisen_kb.lst
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(0154) org 5Ch ;USB Wakeup Interrupt Vector
005C: 7D 20 2D LJMP USBFS_1_WAKEUP_ISR(0155) ljmp _USBFS_1_WAKEUP_ISR
005F: 7E RETI (0156) reti
(0157)
(0158) org 60h ;PSoC I2C Interrupt Vector
(0159) // call void_handler
0060: 7E RETI (0160) reti
0061: 30 HALT
0062: 30 HALT
0063: 30 HALT
(0161)
(0162) org 64h ;Sleep Timer Interrupt Vector
(0163) // call void_handler
0064: 7E RETI (0164) reti
0065: 30 HALT
0066: 30 HALT
0067: 30 HALT
(0165)
(0166) ;-----------------------------------------------------------------------------
(0167) ; Start of Execution.
(0168) ;-----------------------------------------------------------------------------
(0169) ; The Supervisory ROM SWBootReset function has already completed the
(0170) ; calibrate1 process, loading trim values for 5 volt operation.
(0171) ;
(0172) org 68h
(0173) __Start:
(0174)
(0175) ; initialize values for voltage stabilization, if required,
(0176) ; leaving power-on reset (POR) level at the default (low) level, at
(0177) ; least for now.
(0178) ;
0068: 71 10 OR F,16 (0179) M8C_SetBank1
006A: 62 E3 07 MOV REG[227],7 (0180) mov reg[VLT_CR], LVD_TBEN_JUST | TRIP_VOLTAGE_JUST
006D: 70 EF AND F,239 (0181) M8C_SetBank0
(0182)
(0183) ; %53%20%46%46% Apply Erratum 001-05137 workaround
006F: 50 20 MOV A,32 (0184) mov A, 20h
0071: 28 ROMX (0185) romx
(0186) ; %45%20%46%46% End workaround
(0187)
(0188) IF ( WATCHDOG_ENABLE ) ; WDT selected in Global Params
(0189) M8C_EnableWatchDog
(0190) ENDIF
(0191)
0072: 41 FE FB AND REG[254],251 (0192) and reg[CPU_SCR1], ~CPU_SCR1_ECO_ALLOWED ; Prevent ECO from being enabled
(0193)
(0194) ;---------------------------
(0195) ; Set up the Temporary stack
(0196) ;---------------------------
(0197) ; A temporary stack is set up for the SSC instructions.
(0198) ; The real stack start will be assigned later.
(0199) ;
(0200) _stack_start: equ 80h
0075: 50 80 MOV A,128 (0201) mov A, _stack_start ; Set top of stack to end of used RAM
0077: 4E SWAP SP,A (0202) swap SP, A ; This is only temporary if going to LMM
(0203)
(0204) ;------------------------
(0205) ; Set Power-related Trim
(0206) ;------------------------
(0207)
(0208) IF ( POWER_SETTING & POWER_SET_5V0) ; *** 5.0 Volt operation ***
(0209)
(0210) IF ( AGND_BYPASS )
(0211) ;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
(0212) ; The 5V trim has already been set, but we need to update the AGNDBYP
(0213) ; bit in the write-only BDG_TR register. Recalculate the register
(0214) ; value using the proper trim values.
(0215) ;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
(0216) M8SSC_SetTableVoltageTrim 1, SSCTBL1_TRIM_BGR_5V, AGND_BYPASS_JUST
(0217) ENDIF
(0218) ELSE
(0219) ; 3.3V operation trim codes
(0220) ; Set the IMO and Bandgap trims for 3v operation
(0221) M8SSC_SetTableTrims 1, SSCTBL1_TRIM_IMO_3V_24MHZ, SSCTBL1_TRIM_BGR_3V, AGN_BYPASS_JUST
(0222)
(0223) ; Set the IMO Gain Trim for 3v operation
(0224) M8SSC_SetTableIMOGainTrim 2, SSCTBL2_TRIM_IMO_GAIN_3V
(0225)
(0226) ENDIF ; 3.3 Volt Operation
(0227)
0078: 55 F8 00 MOV [248],0 (0228) mov [bSSC_KEY1], 0 ; Lock out Flash and Supervisiory operations
007B: 55 F9 00 MOV [249],0 (0229) mov [bSSC_KEYSP], 0
(0230)
(0231) ;---------------------------------------
(0232) ; Initialize Crystal Oscillator and PLL
(0233) ;---------------------------------------
(0234)
(0235) ; Either no ECO, or waiting for stable clock is to be done in main
007E: 71 10 OR F,16 (0236) M8C_SetBank1
0080: 62 E0 02 MOV REG[224],2 (0237) mov reg[OSC_CR0], (SLEEP_TIMER_JUST | OSC_CR0_CPU_12MHz)
0083: 70 EF AND F,239 (0238) M8C_SetBank0
0085: 62 E3 38 MOV REG[227],56 (0239) M8C_ClearWDTAndSleep ; Reset the watch dog
(0240)
(0241) ;---------------------------------------------
(0242) ; Enter the Large Memory Model, if applicable
(0243) ;---------------------------------------------
(0244) IF ( SYSTEM_LARGE_MEMORY_MODEL )
0088: 62 D1 03 MOV REG[209],3 (0245) RAM_SETPAGE_STK SYSTEM_STACK_PAGE ; relocate stack page ...
008B: 50 00 MOV A,0 (0246) mov A, SYSTEM_STACK_BASE_ADDR ; and offset, if any
008D: 4E SWAP SP,A (0247) swap A, SP
008E: 62 D3 03 MOV REG[211],3 (0248) RAM_SETPAGE_IDX2STK ; initialize other page pointers
0091: 62 D0 00 MOV REG[208],0 (0249) RAM_SETPAGE_CUR 0
0094: 62 D5 00 MOV REG[213],0 (0250) RAM_SETPAGE_MVW 0
0097: 62 D4 00 MOV REG[212],0 (0251) RAM_SETPAGE_MVR 0
(0252)
(0253) IF ( SYSTEM_IDXPG_TRACKS_STK_PP ); Now enable paging:
009A: 71 C0 OR F,192 (0254) or F, FLAG_PGMODE_11b ; LMM w/ IndexPage<==>StackPage
(0255) ELSE
(0256) or F, FLAG_PGMODE_10b ; LMM w/ independent IndexPage
(0257) ENDIF ; SYSTEM_IDXPG_TRACKS_STK_PP
(0258) ELSE
(0259) mov A, __ramareas_end ; Set top of stack to end of used RAM
(0260) swap SP, A
(0261) ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
(0262)
(0263) ;------------------------
(0264) ; Close CT leakage path.
(0265) ;------------------------
009C: 62 71 05 MOV REG[113],5 (0266) mov reg[ACB00CR0], 05h
009F: 62 75 05 MOV REG[117],5 (0267) mov reg[ACB01CR0], 05h
(0268)
(0269) ;-------------------------
(0270) ; Load Base Configuration
(0271) ;-------------------------
(0272) ; Load global parameter settings and load the user modules in the
(0273) ; base configuration. Exceptions: (1) Leave CPU Speed fast as possible
(0274) ; to minimize start up time; (2) We may still need to play with the
(0275) ; Sleep Timer.
(0276) ;
00A2: 7C 04 85 LCALL 0x0485 (0277) lcall LoadConfigInit
00A5: 71 10 OR F,16 (0278) M8C_SetBank1
00A7: 41 E7 3F AND REG[231],63 (0279) and reg[DEC_CR1], 0x3F
00AA: 43 E7 80 OR REG[231],128 (0280) or reg[DEC_CR1], 0x80
00AD: 70 EF AND F,239 (0281) M8C_SetBank0
(0282) ;-----------------------------------
(0283) ; Initialize C Run-Time Environment
(0284) ;-----------------------------------
(0285) IF ( C_LANGUAGE_SUPPORT )
(0286) IF ( SYSTEM_SMALL_MEMORY_MODEL )
(0287) mov A,0 ; clear the 'bss' segment to zero
(0288) mov [__r0],<__bss_start
(0289) BssLoop:
(0290) cmp [__r0],<__bss_end
(0291) jz BssDone
(0292) mvi [__r0],A
(0293) jmp BssLoop
(0294) BssDone:
(0295) mov A,>__idata_start ; copy idata to data segment
(0296) mov X,<__idata_start
(0297) mov [__r0],<__data_start
(0298) IDataLoop:
(0299) cmp [__r0],<__data_end
(0300) jz C_RTE_Done
(0301) push A
(0302) romx
(0303) mvi [__r0],A
(0304) pop A
(0305) inc X
(0306) adc A,0
(0307) jmp IDataLoop
(0308)
(0309) ENDIF ; SYSTEM_SMALL_MEMORY_MODEL
(0310)
(0311) IF ( SYSTEM_LARGE_MEMORY_MODEL )
00AF: 62 D0 00 MOV REG[208],0 (0312) mov reg[CUR_PP], >__r0 ; force direct addr mode instructions
(0313) ; to use the Virtual Register page.
(0314)
(0315) ; Dereference the constant (flash) pointer pXIData to access the start
(0316) ; of the extended idata area, "xidata." Xidata follows the end of the
(0317) ; text segment and may have been relocated by the Code Compressor.
(0318) ;
00B2: 50 02 MOV A,2 (0319) mov A, >__pXIData ; Get the address of the flash
00B4: 57 3E MOV X,62 (0320) mov X, <__pXIData ; pointer to the xidata area.
00B6: 08 PUSH A (0321) push A
00B7: 28 ROMX (0322) romx ; get the MSB of xidata's address
00B8: 53 D5 MOV [__r0],A (0323) mov [__r0], A
00BA: 18 POP A (0324) pop A
00BB: 75 INC X (0325) inc X
00BC: 09 00 ADC A,0 (0326) adc A, 0
00BE: 28 ROMX (0327) romx ; get the LSB of xidata's address
00BF: 4B SWAP A,X (0328) swap A, X
00C0: 51 D5 MOV A,[213] (0329) mov A, [__r0] ; pXIData (in [A,X]) points to the
(0330) ; XIData structure list in flash
00C2: 80 04 JMP 0x00C7 (0331) jmp .AccessStruct
(0332)
(0333) ; Unpack one element in the xidata "structure list" that specifies the
(0334) ; values of C variables. Each structure contains 3 member elements.
(0335) ; The first is a pointer to a contiguous block of RAM to be initial-
(0336) ; ized. Blocks are always 255 bytes or less in length and never cross
(0337) ; RAM page boundaries. The list terminates when the MSB of the pointer
(0338) ; contains 0xFF. There are two formats for the struct depending on the
(0339) ; value in the second member element, an unsigned byte:
(0340) ; (1) If the value of the second element is non-zero, it represents
(0341) ; the 'size' of the block of RAM to be initialized. In this case, the
(0342) ; third member of the struct is an array of bytes of length 'size' and
(0343) ; the bytes are copied to the block of RAM.
(0344) ; (2) If the value of the second element is zero, the block of RAM is
(0345) ; to be cleared to zero. In this case, the third member of the struct
(0346) ; is an unsigned byte containing the number of bytes to clear.
(0347)
(0348) .AccessNextStructLoop:
00C4: 75 INC X (0349) inc X ; pXIData++
00C5: 09 00 ADC A,0 (0350) adc A, 0
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