📄 c2cx0032.lst
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131 006c bb1f RPT #N-1
132 006d a8f0 BLDD #ADRESULT+384,*BR0+
006e 0180!
133 006f 7980 B STAGE1
0070 0087+
134
135 0071 ba01 FFTM: SUB #1
136 0072 e308 BCND FFTN,NEQ
0073 0079+
137 0074 bb1f RPT #N-1
138 0075 a8f0 BLDD #ADRESULT+416,*BR0+
0076 01a0!
139 0077 7980 B STAGE1
0078 0087+
140
141 0079 ba01 FFTN: SUB #1
142 007a e308 BCND FFTO,NEQ
007b 0081+
143 007c bb1f RPT #N-1
144 007d a8f0 BLDD #ADRESULT+448,*BR0+
007e 01c0!
145 007f 7980 B STAGE1
0080 0087+
146
147 0081 ba01 FFTO: SUB #1
148 0082 e308 BCND FFTB,NEQ
0083 0019+
149 0084 bb1f RPT #N-1
150 0085 a8f0 BLDD #ADRESULT+480,*BR0+
0086 01e0!
151
152 ; FFT CODE for STAGES 1 and 2 / ARP=AR3
153 ;
154 0087 STAGE1:
155 0087 bc06 LDP #6
156 0088 b007 lar ar0,#7 ; indexregister = 7
157 0089 0101- lar ar1,DATAADD ; pointer to DATA r1,i1
158 008a 0202- lar ar2,DATA2 ; pointer to DATA + 2 r2,i2
159 008b 0303- lar ar3,DATA4 ; pointer to DATA + 4 r3,i3
160 008c 0404- lar ar4,DATA6 ; pointer to DATA + 6 r4,i4
161 008d COMBO2X 8 ; repeat 8 times
1 008d b701 LAR AR7,#8/divid-1
1 008e+ loopc: .set $
1
1 $if divid=4
1 008e combo2y 3
2 ; ARP AR1 AR2 AR3 AR4 AR5
2 ; --- --- --- --- --- ---
2 008e 1e8c LACC *,14,AR4 ; ACC := (R3)/4 4 R1 R2 R3 R4 T1
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00 Sat Jul 14 16:18:01 2001
Copyright (c) 1987-1999 Texas Instruments Incorporated
0032 point DIT Radix-2, Complex FFT PAGE 5
2 008f 3e8d SUB *,14,AR5 ; ACC := (R3+R4)/4 5 R1 R2 R3 R4 T1
2 0090 99ac SACH *+,1,AR4 ; T1 = (R3-R4)/2 4 R1 R2 I3 R4 T2
2 ;
2 0091 2fad ADD *+,15,AR5 ; ACC := (R3+R4)/4 5 R1 R2 R3 I4 T2
2 0092 998a SACH *,1,AR2 ; T2 = (R3+R4)/2 2 R1 R2 R3 I4 T2
2 ;
2 0093 2e89 ADD *,14,AR1 ; ACC := (R2+R3+R4)/4 1 R1 R2 R3 I4 T2
2 0094 2e80 ADD *,14 ; ACC := (R1+R2+R3+R4)/4 1 R1 R2 R3 I4 T2
2 0095 98ad SACH *+,0,AR5 ; R1 := (R1+R2+R3+R4)/4 5 I1 R2 R3 I4 T2
2 0096 658b SUB *,16,AR3 ; ACC := (R1+R2-(R3+R4))/4 3 I1 R2 R3 I4 T2
2 0097 98ad SACH *+,0,AR5 ; R3 := (R1+R2-(R3+R4))/4 5 I1 R2 I3 I4 T2
2 ;
2 0098 2f8a ADD *,15,AR2 ; ACC := (R1+R2)/4 2 I1 R2 I3 I4 T2
2 0099 3f8b SUB *,15,AR3 ; ACC := (R1-R2)/4 3 I1 R2 I3 I4 T2
2 009a 2e8c ADD *,14,AR4 ; ACC := ((R1-R2)+(I3))/4 4 I1 R2 I3 I4 T2
2 009b 3e8a SUB *,14,AR2 ; ACC := ((R1-R2)+(I3-I4))/4 2 I1 R2 I3 I4 T2
2 009c 98ac SACH *+,0,AR4 ; R2 := ((R1-R2)+(I3-I4))/4 4 I1 I2 I3 I4 T2
2 009d 2f9b ADD *-,15,AR3 ; ACC := ((R1-R2)+ I3+I4 )/4 3 I1 I2 I3 R4 T2
2 009e 3f8c SUB *,15,AR4 ; ACC := ((R1-R2)-(I3-I4))/4 4 I1 I2 I3 R4 T2
2 009f 98a9 SACH *+,0,AR1 ; R4 := ((R1-R2)-(I3-I4))/4 1 I1 I2 I3 I4 T2
2 ;
2 00a0 1e8a LACC *,14,AR2 ; ACC := (I1)/4 2 I1 I2 I3 I4 T2
2 00a1 3e8d SUB *,14,AR5 ; ACC := (I1-I2)/4 5 I1 I2 I3 I4 T2
2 00a2 998a SACH *,1,AR2 ; T2 := (I1-I2)/2 2 I1 I2 I3 I4 T2
2 00a3 2f8b ADD *,15,AR3 ; ACC := ((I1+I2))/4 4 I1 I2 I3 I4 T2
2 00a4 2e8c ADD *,14,AR4 ; ACC := ((I1+I2)+(I3))/4 4 I1 I2 I3 I4 T2
2 00a5 2e89 ADD *,14,AR1 ; ACC := ((I1+I2)+(I3+I4))/4 1 I1 I2 I3 I4 T2
2 00a6 98eb SACH *0+,0,AR3 ; I1 := ((I1+I2)+(I3+I4))/4 3 R5 I2 I3 I4 T2
2 00a7 3f8c SUB *,15,AR4 ; ACC := ((I1+I2)-(I3+I4))/4 4 R5 I2 I3 I4 T2
2 00a8 3f8b SUB *,15,AR3 ; ACC := ((I1+I2)-(I3+I4))/4 3 R5 I2 I3 I4 T2
2 00a9 98ed SACH *0+,0,AR5 ; I3 := ((I1+I2)-(I3+I4))/4 5 R5 I2 R7 I4 T2
2 ;
2 00aa 1f90 LACC *-,15 ; ACC := (I1-I2)/4 5 R5 I2 R7 I4 T1
2 00ab 3f8a SUB *,15,AR2 ; ACC := ((I1-I2)-(R3-R4))/4 2 R5 I2 R7 I4 T1
2 00ac 98ed SACH *0+,0,AR5 ; I2 := ((I1-I2)-(R3-R4))/4 5 R5 R6 R7 I4 T1
2 00ad 618c ADD *,16,AR4 ; ACC := ((I1-I2)+(R3-R4))/4 4 R5 R6 R7 I4 T1
2 00ae 98eb SACH *0+,0,AR3 ; I4 := ((I1-I2)+(R3-R4))/4 3 R5 R6 R7 R8 T1
2 ;
1 00af combo2y 3
2 ; ARP AR1 AR2 AR3 AR4 AR5
2 ; --- --- --- --- --- ---
2 00af 1e8c LACC *,14,AR4 ; ACC := (R3)/4 4 R1 R2 R3 R4 T1
2 00b0 3e8d SUB *,14,AR5 ; ACC := (R3+R4)/4 5 R1 R2 R3 R4 T1
2 00b1 99ac SACH *+,1,AR4 ; T1 = (R3-R4)/2 4 R1 R2 I3 R4 T2
2 ;
2 00b2 2fad ADD *+,15,AR5 ; ACC := (R3+R4)/4 5 R1 R2 R3 I4 T2
2 00b3 998a SACH *,1,AR2 ; T2 = (R3+R4)/2 2 R1 R2 R3 I4 T2
2 ;
2 00b4 2e89 ADD *,14,AR1 ; ACC := (R2+R3+R4)/4 1 R1 R2 R3 I4 T2
2 00b5 2e80 ADD *,14 ; ACC := (R1+R2+R3+R4)/4 1 R1 R2 R3 I4 T2
2 00b6 98ad SACH *+,0,AR5 ; R1 := (R1+R2+R3+R4)/4 5 I1 R2 R3 I4 T2
2 00b7 658b SUB *,16,AR3 ; ACC := (R1+R2-(R3+R4))/4 3 I1 R2 R3 I4 T2
2 00b8 98ad SACH *+,0,AR5 ; R3 := (R1+R2-(R3+R4))/4 5 I1 R2 I3 I4 T2
2 ;
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00 Sat Jul 14 16:18:01 2001
Copyright (c) 1987-1999 Texas Instruments Incorporated
0032 point DIT Radix-2, Complex FFT PAGE 6
2 00b9 2f8a ADD *,15,AR2 ; ACC := (R1+R2)/4 2 I1 R2 I3 I4 T2
2 00ba 3f8b SUB *,15,AR3 ; ACC := (R1-R2)/4 3 I1 R2 I3 I4 T2
2 00bb 2e8c ADD *,14,AR4 ; ACC := ((R1-R2)+(I3))/4 4 I1 R2 I3 I4 T2
2 00bc 3e8a SUB *,14,AR2 ; ACC := ((R1-R2)+(I3-I4))/4 2 I1 R2 I3 I4 T2
2 00bd 98ac SACH *+,0,AR4 ; R2 := ((R1-R2)+(I3-I4))/4 4 I1 I2 I3 I4 T2
2 00be 2f9b ADD *-,15,AR3 ; ACC := ((R1-R2)+ I3+I4 )/4 3 I1 I2 I3 R4 T2
2 00bf 3f8c SUB *,15,AR4 ; ACC := ((R1-R2)-(I3-I4))/4 4 I1 I2 I3 R4 T2
2 00c0 98a9 SACH *+,0,AR1 ; R4 := ((R1-R2)-(I3-I4))/4 1 I1 I2 I3 I4 T2
2 ;
2 00c1 1e8a LACC *,14,AR2 ; ACC := (I1)/4 2 I1 I2 I3 I4 T2
2 00c2 3e8d SUB *,14,AR5 ; ACC := (I1-I2)/4 5 I1 I2 I3 I4 T2
2 00c3 998a SACH *,1,AR2 ; T2 := (I1-I2)/2 2 I1 I2 I3 I4 T2
2 00c4 2f8b ADD *,15,AR3 ; ACC := ((I1+I2))/4 4 I1 I2 I3 I4 T2
2 00c5 2e8c ADD *,14,AR4 ; ACC := ((I1+I2)+(I3))/4 4 I1 I2 I3 I4 T2
2 00c6 2e89 ADD *,14,AR1 ; ACC := ((I1+I2)+(I3+I4))/4 1 I1 I2 I3 I4 T2
2 00c7 98eb SACH *0+,0,AR3 ; I1 := ((I1+I2)+(I3+I4))/4 3 R5 I2 I3 I4 T2
2 00c8 3f8c SUB *,15,AR4 ; ACC := ((I1+I2)-(I3+I4))/4 4 R5 I2 I3 I4 T2
2 00c9 3f8b SUB *,15,AR3 ; ACC := ((I1+I2)-(I3+I4))/4 3 R5 I2 I3 I4 T2
2 00ca 98ed SACH *0+,0,AR5 ; I3 := ((I1+I2)-(I3+I4))/4 5 R5 I2 R7 I4 T2
2 ;
2 00cb 1f90 LACC *-,15 ; ACC := (I1-I2)/4 5 R5 I2 R7 I4 T1
2 00cc 3f8a SUB *,15,AR2 ; ACC := ((I1-I2)-(R3-R4))/4 2 R5 I2 R7 I4 T1
2 00cd 98ed SACH *0+,0,AR5 ; I2 := ((I1-I2)-(R3-R4))/4 5 R5 R6 R7 I4 T1
2 00ce 618c ADD *,16,AR4 ; ACC := ((I1-I2)+(R3-R4))/4 4 R5 R6 R7 I4 T1
2 00cf 98eb SACH *0+,0,AR3 ; I4 := ((I1-I2)+(R3-R4))/4 3 R5 R6 R7 R8 T1
2 ;
1 $endif
1
1 $if divid=8
1 combo2y 3
1 combo2y 3
1 combo2y 3
1 combo2y 3
1 combo2y 3
1 combo2y 3
1 $endif
1
1 00d0 combo2y 3
2 ; ARP AR1 AR2 AR3 AR4 AR5
2 ; --- --- --- --- --- ---
2 00d0 1e8c LACC *,14,AR4 ; ACC := (R3)/4 4 R1 R2 R3 R4 T1
2 00d1 3e8d SUB *,14,AR5 ; ACC := (R3+R4)/4 5 R1 R2 R3 R4 T1
2 00d2 99ac SACH *+,1,AR4 ; T1 = (R3-R4)/2 4 R1 R2 I3 R4 T2
2 ;
2 00d3 2fad ADD *+,15,AR5 ; ACC := (R3+R4)/4 5 R1 R2 R3 I4 T2
2 00d4 998a SACH *,1,AR2 ; T2 = (R3+R4)/2 2 R1 R2 R3 I4 T2
2 ;
2 00d5 2e89 ADD *,14,AR1 ; ACC := (R2+R3+R4)/4 1 R1 R2 R3 I4 T2
2 00d6 2e80 ADD *,14 ; ACC := (R1+R2+R3+R4)/4 1 R1 R2 R3 I4 T2
2 00d7 98ad SACH *+,0,AR5 ; R1 := (R1+R2+R3+R4)/4 5 I1 R2 R3 I4 T2
2 00d8 658b SUB *,16,AR3 ; ACC := (R1+R2-(R3+R4))/4 3 I1 R2 R3 I4 T2
2 00d9 98ad SACH *+,0,AR5 ; R3 := (R1+R2-(R3+R4))/4 5 I1 R2 I3 I4 T2
2 ;
2 00da 2f8a ADD *,15,AR2 ; ACC := (R1+R2)/4 2 I1 R2 I3 I4 T2
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00 Sat Jul 14 16:18:01 2001
Copyright (c) 1987-1999 Texas Instruments Incorporated
0032 point DIT Radix-2, Complex FFT PAGE 7
2 00db 3f8b SUB *,15,AR3 ; ACC := (R1-R2)/4 3 I1 R2 I3 I4 T2
2 00dc 2e8c ADD *,14,AR4 ; ACC := ((R1-R2)+(I3))/4 4 I1 R2 I3 I4 T2
2 00dd 3e8a SUB *,14,AR2 ; ACC := ((R1-R2)+(I3-I4))/4 2 I1 R2 I3 I4 T2
2 00de 98ac SACH *+,0,AR4 ; R2 := ((R1-R2)+(I3-I4))/4 4 I1 I2 I3 I4 T2
2 00df 2f9b ADD *-,15,AR3 ; ACC := ((R1-R2)+ I3+I4 )/4 3 I1 I2 I3 R4 T2
2 00e0 3f8c SUB *,15,AR4 ; ACC := ((R1-R2)-(I3-I4))/4 4 I1 I2 I3 R4 T2
2 00e1 98a9 SACH *+,0,AR1 ; R4 := ((R1-R2)-(I3-I4))/4 1 I1 I2 I3 I4 T2
2 ;
2 00e2 1e8a LACC *,14,AR2 ; ACC := (I1)/4 2 I1 I2 I3 I4 T2
2 00e3 3e8d SUB *,14,AR5 ; ACC := (I1-I2)/4 5 I1 I2 I3 I4 T2
2 00e4 998a SACH *,1,AR2 ; T2 := (I1-I2)/2 2 I1 I2 I3 I4 T2
2 00e5 2f8b ADD *,15,AR3 ; ACC := ((I1+I2))/4 4 I1 I2 I3 I4 T2
2 00e6 2e8c ADD *,14,AR4 ; ACC := ((I1+I2)+(I3))/4 4 I1 I2 I3 I4 T2
2 00e7 2e89 ADD *,14,AR1 ; ACC := ((I1+I2)+(I3+I4))/4 1 I1 I2 I3 I4 T2
2 00e8 98eb SACH *0+,0,AR3 ; I1 := ((I1+I2)+(I3+I4))/4 3 R5 I2 I3 I4 T2
2 00e9 3f8c SUB *,15,AR4 ; ACC := ((I1+I2)-(I3+I4))/4 4 R5 I2 I3 I4 T2
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