adc.map.qmsg

模数转换器AD976采样控制器程序Verilog实现

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version " "Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 22 16:42:35 2008 " "Info: Processing started: Fri Feb 22 16:42:35 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ADC -c ADC " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ADC -c ADC" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ADC.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ADC.v" { { "Info" "ISGN_ENTITY_NAME" "1 ADC " "Info: Found entity 1: ADC" {  } { { "ADC.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ADCcaiyang/ADC.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "ADC " "Info: Elaborating entity \"ADC\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 ADC.v(34) " "Warning (10230): Verilog HDL assignment warning at ADC.v(34): truncated value with size 32 to match size of target (16)" {  } { { "ADC.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ADCcaiyang/ADC.v" 34 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 ADC.v(45) " "Warning (10230): Verilog HDL assignment warning at ADC.v(45): truncated value with size 32 to match size of target (16)" {  } { { "ADC.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ADCcaiyang/ADC.v" 45 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 ADC.v(53) " "Warning (10230): Verilog HDL assignment warning at ADC.v(53): truncated value with size 32 to match size of target (16)" {  } { { "ADC.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ADCcaiyang/ADC.v" 53 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 ADC.v(59) " "Warning (10230): Verilog HDL assignment warning at ADC.v(59): truncated value with size 32 to match size of target (16)" {  } { { "ADC.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ADCcaiyang/ADC.v" 59 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 ADC.v(69) " "Warning (10230): Verilog HDL assignment warning at ADC.v(69): truncated value with size 32 to match size of target (16)" {  } { { "ADC.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ADCcaiyang/ADC.v" 69 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "trans ADC.v(12) " "Warning (10034): Output port \"trans\" at ADC.v(12) has no driver" {  } { { "ADC.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ADCcaiyang/ADC.v" 12 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "Dout\[3\] ADC.v(13) " "Warning (10034): Output port \"Dout\[3\]\" at ADC.v(13) has no driver" {  } { { "ADC.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ADCcaiyang/ADC.v" 13 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "Dout\[2\] ADC.v(13) " "Warning (10034): Output port \"Dout\[2\]\" at ADC.v(13) has no driver" {  } { { "ADC.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ADCcaiyang/ADC.v" 13 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "Dout\[1\] ADC.v(13) " "Warning (10034): Output port \"Dout\[1\]\" at ADC.v(13) has no driver" {  } { { "ADC.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ADCcaiyang/ADC.v" 13 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "Dout\[0\] ADC.v(13) " "Warning (10034): Output port \"Dout\[0\]\" at ADC.v(13) has no driver" {  } { { "ADC.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ADCcaiyang/ADC.v" 13 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "Dout\[0\] GND " "Warning: Pin \"Dout\[0\]\" stuck at GND" {  } { { "ADC.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ADCcaiyang/ADC.v" 13 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "Dout\[1\] GND " "Warning: Pin \"Dout\[1\]\" stuck at GND" {  } { { "ADC.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ADCcaiyang/ADC.v" 13 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "Dout\[2\] GND " "Warning: Pin \"Dout\[2\]\" stuck at GND" {  } { { "ADC.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ADCcaiyang/ADC.v" 13 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "Dout\[3\] GND " "Warning: Pin \"Dout\[3\]\" stuck at GND" {  } { { "ADC.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ADCcaiyang/ADC.v" 13 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "trans GND " "Warning: Pin \"trans\" stuck at GND" {  } { { "ADC.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ADCcaiyang/ADC.v" 12 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "4 " "Warning: Design contains 4 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "Din\[0\] " "Warning: No output dependent on input pin \"Din\[0\]\"" {  } { { "ADC.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ADCcaiyang/ADC.v" 10 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "Din\[1\] " "Warning: No output dependent on input pin \"Din\[1\]\"" {  } { { "ADC.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ADCcaiyang/ADC.v" 10 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "Din\[2\] " "Warning: No output dependent on input pin \"Din\[2\]\"" {  } { { "ADC.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ADCcaiyang/ADC.v" 10 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "Din\[3\] " "Warning: No output dependent on input pin \"Din\[3\]\"" {  } { { "ADC.v" "" { Text "C:/Documents and Settings/Administrator/桌面/ADCcaiyang/ADC.v" 10 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "67 " "Info: Implemented 67 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "7 " "Info: Implemented 7 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "55 " "Info: Implemented 55 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 21 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 21 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 22 16:42:38 2008 " "Info: Processing ended: Fri Feb 22 16:42:38 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}