adc.v

来自「模数转换器AD976采样控制器程序Verilog实现」· Verilog 代码 · 共 72 行

module ADC(Din,clk,R_nC,nCS,Dout,trans);
				//Din:AD输出的16位数据，即FPGA接收到的数据
				//clk:时钟信号
				//R_nC:读/转换信号
				//nCS:片选信号
				//Dout:输出的数据
				//trans:数据输出信号，下降沿数据有效
	
input clk;      
input [3:0] Din; //16位并行数据输入

output R_nC,nCS,trans;  //R_nC为读_转换信号，nCS为片选信号，低有效
output [3:0] Dout;//16位数据输出

reg [3:0] Dout;
reg R_nC,nCS,trans;
reg [3:0] current_state;
reg [15:0] count1;
reg [15:0] count2;
//定义状态
parameter delay=9;
parameter n_CS_low=49; 
parameter n_CS_high=1999;
parameter R_nC_low=59; 
parameter R_nC_high=3999;

always @(posedge clk)
begin
	if(count1>=R_nC_low)
	begin
		if(count1<=R_nC_high)
			begin
			R_nC<=1;
			count1<=count1+1;
			end
		else
			begin
			count1<=0; 
			end
	end

	else
	begin
	R_nC<=0;
	count1<=count1+1;
	end
	//nCS信号
	if(count2>=delay)
	begin
		if(count2<=n_CS_low)
			begin
			nCS<=0;
			count2<=count2+1;
			end
		else
			if(count2<=n_CS_high)
			begin
			nCS<=1;
			count2<=count2+1;
			end
			else
			begin
			count2<=0;
			end
	end
	else
	begin
	nCS<=1;
	count2<=count2+1;
	end	
end	
endmodule