adc.sim.rpt

模数转换器AD976采样控制器程序Verilog实现

; |ADC|nCS~529       ; |ADC|nCS~529                ; combout          ;
; |ADC|count2[3]     ; |ADC|count2[3]~522COUT1_532 ; cout1            ;
; |ADC|count2[1]     ; |ADC|count2[1]~523          ; cout0            ;
; |ADC|count2[1]     ; |ADC|count2[1]~523COUT1_531 ; cout1            ;
; |ADC|count2[2]     ; |ADC|count2[2]~524          ; cout             ;
; |ADC|count2[0]     ; |ADC|count2[0]~525          ; cout0            ;
; |ADC|count2[0]     ; |ADC|count2[0]~525COUT1_530 ; cout1            ;
; |ADC|nCS~530       ; |ADC|nCS~530                ; combout          ;
; |ADC|nCS~531       ; |ADC|nCS~531                ; combout          ;
; |ADC|nCS~532       ; |ADC|nCS~532                ; combout          ;
; |ADC|nCS~533       ; |ADC|nCS~533                ; combout          ;
; |ADC|LessThan3~221 ; |ADC|LessThan3~221          ; combout          ;
; |ADC|nCS~535       ; |ADC|nCS~535                ; combout          ;
; |ADC|LessThan3~222 ; |ADC|LessThan3~222          ; combout          ;
; |ADC|count2~528    ; |ADC|count2~528             ; combout          ;
; |ADC|clk           ; |ADC|clk                    ; combout          ;
; |ADC|R_nC          ; |ADC|R_nC                   ; padio            ;
; |ADC|nCS           ; |ADC|nCS                    ; padio            ;
+--------------------+-----------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+----------------------------------------------------------------------+
; Missing 1-Value Coverage                                             ;
+--------------------+------------------------------+------------------+
; Node Name          ; Output Port Name             ; Output Port Type ;
+--------------------+------------------------------+------------------+
; |ADC|count1[9]     ; |ADC|count1[9]~299COUT1_323  ; cout1            ;
; |ADC|count1[8]     ; |ADC|count1[8]~301COUT1_322  ; cout1            ;
; |ADC|count1[6]     ; |ADC|count1[6]~302           ; cout0            ;
; |ADC|count1[5]     ; |ADC|count1[5]~303           ; cout0            ;
; |ADC|count1[10]    ; |ADC|count1[10]~304COUT1_324 ; cout1            ;
; |ADC|count1[11]    ; |ADC|count1[11]~305COUT1_325 ; cout1            ;
; |ADC|count1[12]    ; |ADC|count1[12]~306          ; cout             ;
; |ADC|count1[13]    ; |ADC|count1[13]~307          ; cout0            ;
; |ADC|count1[13]    ; |ADC|count1[13]~307COUT1_326 ; cout1            ;
; |ADC|count1[14]    ; |ADC|count1[14]~308          ; cout0            ;
; |ADC|count1[14]    ; |ADC|count1[14]~308COUT1_327 ; cout1            ;
; |ADC|LessThan0~262 ; |ADC|LessThan0~262           ; combout          ;
; |ADC|count1[3]     ; |ADC|count1[3]~310           ; cout0            ;
; |ADC|count1[4]     ; |ADC|count1[4]~311           ; cout0            ;
; |ADC|count2[11]    ; |ADC|count2[11]~512          ; cout0            ;
; |ADC|count2[11]    ; |ADC|count2[11]~512COUT1_539 ; cout1            ;
; |ADC|count2[12]    ; |ADC|count2[12]~513          ; cout             ;
; |ADC|count2[13]    ; |ADC|count2[13]~514          ; cout0            ;
; |ADC|count2[13]    ; |ADC|count2[13]~514COUT1_540 ; cout1            ;
; |ADC|LessThan4~257 ; |ADC|LessThan4~257           ; combout          ;
; |ADC|count2[6]     ; |ADC|count2[6]~515           ; cout0            ;
; |ADC|count2[8]     ; |ADC|count2[8]~516COUT1_536  ; cout1            ;
; |ADC|count2[9]     ; |ADC|count2[9]~517COUT1_537  ; cout1            ;
; |ADC|count2[10]    ; |ADC|count2[10]~518COUT1_538 ; cout1            ;
; |ADC|count2[5]     ; |ADC|count2[5]~520           ; cout0            ;
; |ADC|count2[4]     ; |ADC|count2[4]~521           ; cout0            ;
; |ADC|count2[3]     ; |ADC|count2[3]~522           ; cout0            ;
; |ADC|count2[14]    ; |ADC|count2[14]~526          ; cout0            ;
; |ADC|count2[14]    ; |ADC|count2[14]~526COUT1_541 ; cout1            ;
; |ADC|nCS~534       ; |ADC|nCS~534                 ; combout          ;
; |ADC|Dout[0]       ; |ADC|Dout[0]                 ; padio            ;
; |ADC|Dout[1]       ; |ADC|Dout[1]                 ; padio            ;
; |ADC|Dout[2]       ; |ADC|Dout[2]                 ; padio            ;
; |ADC|Dout[3]       ; |ADC|Dout[3]                 ; padio            ;
; |ADC|trans         ; |ADC|trans                   ; padio            ;
+--------------------+------------------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+----------------------------------------------------------------------+
; Missing 0-Value Coverage                                             ;
+--------------------+------------------------------+------------------+
; Node Name          ; Output Port Name             ; Output Port Type ;
+--------------------+------------------------------+------------------+
; |ADC|count1[9]     ; |ADC|count1[9]~299COUT1_323  ; cout1            ;
; |ADC|count1[8]     ; |ADC|count1[8]~301COUT1_322  ; cout1            ;
; |ADC|count1[6]     ; |ADC|count1[6]~302           ; cout0            ;
; |ADC|count1[5]     ; |ADC|count1[5]~303           ; cout0            ;
; |ADC|count1[10]    ; |ADC|count1[10]~304COUT1_324 ; cout1            ;
; |ADC|count1[11]    ; |ADC|count1[11]~305COUT1_325 ; cout1            ;
; |ADC|count1[12]    ; |ADC|count1[12]~306          ; cout             ;
; |ADC|count1[13]    ; |ADC|count1[13]~307          ; cout0            ;
; |ADC|count1[13]    ; |ADC|count1[13]~307COUT1_326 ; cout1            ;
; |ADC|count1[14]    ; |ADC|count1[14]~308          ; cout0            ;
; |ADC|count1[14]    ; |ADC|count1[14]~308COUT1_327 ; cout1            ;
; |ADC|LessThan0~262 ; |ADC|LessThan0~262           ; combout          ;
; |ADC|count1[3]     ; |ADC|count1[3]~310           ; cout0            ;
; |ADC|count1[4]     ; |ADC|count1[4]~311           ; cout0            ;
; |ADC|count2[11]    ; |ADC|count2[11]~512          ; cout0            ;
; |ADC|count2[11]    ; |ADC|count2[11]~512COUT1_539 ; cout1            ;
; |ADC|count2[12]    ; |ADC|count2[12]~513          ; cout             ;
; |ADC|count2[13]    ; |ADC|count2[13]~514          ; cout0            ;
; |ADC|count2[13]    ; |ADC|count2[13]~514COUT1_540 ; cout1            ;
; |ADC|LessThan4~257 ; |ADC|LessThan4~257           ; combout          ;
; |ADC|count2[6]     ; |ADC|count2[6]~515           ; cout0            ;
; |ADC|count2[8]     ; |ADC|count2[8]~516COUT1_536  ; cout1            ;
; |ADC|count2[9]     ; |ADC|count2[9]~517COUT1_537  ; cout1            ;
; |ADC|count2[10]    ; |ADC|count2[10]~518COUT1_538 ; cout1            ;
; |ADC|count2[5]     ; |ADC|count2[5]~520           ; cout0            ;
; |ADC|count2[4]     ; |ADC|count2[4]~521           ; cout0            ;
; |ADC|count2[3]     ; |ADC|count2[3]~522           ; cout0            ;
; |ADC|count2[14]    ; |ADC|count2[14]~526          ; cout0            ;
; |ADC|count2[14]    ; |ADC|count2[14]~526COUT1_541 ; cout1            ;
; |ADC|nCS~534       ; |ADC|nCS~534                 ; combout          ;
; |ADC|Dout[0]       ; |ADC|Dout[0]                 ; padio            ;
; |ADC|Dout[1]       ; |ADC|Dout[1]                 ; padio            ;
; |ADC|Dout[2]       ; |ADC|Dout[2]                 ; padio            ;
; |ADC|Dout[3]       ; |ADC|Dout[3]                 ; padio            ;
; |ADC|trans         ; |ADC|trans                   ; padio            ;
+--------------------+------------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Sun Mar 16 20:06:52 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off ADC -c ADC
Warning: Can't find signal in vector source file for input pin "|ADC|Din[0]"
Warning: Can't find signal in vector source file for input pin "|ADC|Din[1]"
Warning: Can't find signal in vector source file for input pin "|ADC|Din[2]"
Warning: Can't find signal in vector source file for input pin "|ADC|Din[3]"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      57.83 %
Info: Number of transitions in simulation is 689771
Info: Vector file ADC.sim.vwf is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help.
Info: Quartus II Simulator was successful. 0 errors, 4 warnings
    Info: Processing ended: Sun Mar 16 20:07:09 2008
    Info: Elapsed time: 00:00:17