pblcd_map.mrp

来自「FPGA 基于PICOBLAZE内核的LCD显示程序,完整,XILINX」· MRP 代码 · 共 256 行

Release 8.1i Map I.24
Xilinx Mapping Report File for Design 'PBLCD'

Design Information
------------------
Command Line   : D:\Xilinx\bin\nt\map.exe -ise D:/work/vhdl/PBLCD/PBLCD.ise
-intstyle ise -p xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -o PBLCD_map.ncd
PBLCD.ngd PBLCD.pcf 
Target Device  : xc3s200
Target Package : ft256
Target Speed   : -4
Mapper Version : spartan3 -- $Revision: 1.34 $
Mapped Date    : Sun Mar 18 11:40:19 2007

Design Summary
--------------
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:          69 out of   3,840    1%
  Number of 4 input LUTs:             102 out of   3,840    2%
Logic Distribution:
  Number of occupied Slices:                           91 out of   1,920    4%
    Number of Slices containing only related logic:      91 out of      91  100%
    Number of Slices containing unrelated logic:          0 out of      91    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:            172 out of   3,840    4%
  Number used as logic:                102
  Number used as a route-thru:           2
  Number used for Dual Port RAMs:       16
    (Two LUTs used per Dual Port RAM)
  Number used for 32x1 RAMs:            52
    (Two LUTs used per 32x1 RAM)
  Number of bonded IOBs:                8 out of     173    4%
    IOB Flip Flops:                     7
  Number of Block RAMs:                1 out of      12    8%
  Number of GCLKs:                     1 out of       8   12%

Total equivalent gate count for design:  74,793
Additional JTAG gate count for IOBs:  384
Peak Memory Usage:  133 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Additional Device Resource Counts

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------

Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
   Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
   BUFGP symbol "clk_BUFGP" (output signal=clk_BUFGP)
INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs in the
   schematic.

Section 4 - Removed Logic Summary
---------------------------------
   7 block(s) removed
  11 block(s) optimized away
   8 signal(s) removed

Section 5 - Removed Logic
-------------------------

The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections.  If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented.  This
indentation will be repeated as a chain of related logic is removed.

To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).

Loadless block "processor/read_strobe_flop" (SFF) removed.
 The signal "processor/read_active" is loadless and has been removed.
  Loadless block "processor/read_active_lut" (ROM) removed.

The trimmed logic reported below is either:
   1. part of a cycle
   2. part of disabled logic
   3. a side-effect of other trimmed logic

The signal "processor/interrupt_ack" is unused and has been removed.
 Unused block "processor/ack_flop" (FF) removed.
The signal "processor/sel_shadow_carry" is unused and has been removed.
 Unused block "processor/sel_shadow_carry_lut" (ROM) removed.
The signal "processor/int_pulse" is unused and has been removed.
The signal "processor/int_enable_value" is unused and has been removed.
 Unused block "processor/int_value_lut" (ROM) removed.
The signal "processor/int_enable" is unused and has been removed.
 Unused block "processor/int_enable_flop" (SFF) removed.
  The signal "processor/int_update_enable" is unused and has been removed.
   Unused block "processor/int_update_lut" (ROM) removed.
The signal "processor/not_active_interrupt" is unused and has been removed.

Optimized Block(s):
TYPE 		BLOCK
GND 		XST_GND
VCC 		XST_VCC
LUT1 		interrupt_rt
LUT1 		interrupt_rt1
FDR 		processor/int_capture_flop
   optimized to 0
FDR 		processor/int_flop
   optimized to 0
LUT4 		processor/int_pulse_lut
FDE 		processor/shadow_carry_flop
   optimized to 0
FDE 		processor/shadow_zero_flop
   optimized to 0
INV 		processor/stack_count_inv
MUXCY 		processor/sel_shadow_muxcy

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------

+------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   |
|                                    |         |           |             | Strength | Rate |          |          | Delay |
+------------------------------------------------------------------------------------------------------------------------+
| clk                                | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
| lcd_d<4>                           | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF1     |          |       |
| lcd_d<5>                           | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF1     |          |       |
| lcd_d<6>                           | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF1     |          |       |
| lcd_d<7>                           | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF1     |          |       |
| lcd_e                              | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF1     |          |       |
| lcd_rs                             | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF1     |          |       |
| lcd_rw                             | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF1     |          |       |
+------------------------------------------------------------------------------------------------------------------------+

Section 7 - RPMs
----------------

Section 8 - Guide Report
------------------------
Guide not run on this design.

Section 9 - Area Group Summary
------------------------------
No area groups were found in this design.

Section 10 - Modular Design Summary
-----------------------------------
Modular Design not used for this design.

Section 11 - Timing Report
--------------------------
This design was not run using timing mode.

Section 12 - Configuration String Details
--------------------------
Use the "-detail" map option to print out Configuration Strings

Section 13 - Additional Device Resource Counts
----------------------------------------------
Number of JTAG Gates for IOBs = 8
Number of Equivalent Gates for Design = 74,793
Number of RPM Macros = 0
Number of Hard Macros = 0
DCIRESETs = 0
CAPTUREs = 0
BSCANs = 0
STARTUPs = 0
DCMs = 0
GCLKs = 1
ICAPs = 0
18X18 Multipliers = 0
Block RAMs = 1
Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 46
IOB Dual-Rate Flops not driven by LUTs = 0
IOB Dual-Rate Flops = 0
IOB Slave Pads = 0
IOB Master Pads = 0
IOB Latches not driven by LUTs = 0
IOB Latches = 0
IOB Flip Flops not driven by LUTs = 0
IOB Flip Flops = 7
Unbonded IOBs = 0
Bonded IOBs = 8
XORs = 37
CARRY_INITs = 23
CARRY_SKIPs = 0
CARRY_MUXes = 38
Shift Registers = 0
Static Shift Registers = 0
Dynamic Shift Registers = 0
16x1 ROMs = 0
16x1 RAMs = 0
32x1 RAMs = 26
Dual Port RAMs = 8
MUXFs = 43
MULT_ANDs = 0
4 input LUTs used as Route-Thrus = 2
4 input LUTs = 102
Slice Latches not driven by LUTs = 0
Slice Latches = 0
Slice Flip Flops not driven by LUTs = 46
Slice Flip Flops = 69
SliceMs = 34
SliceLs = 57
Slices = 91
F6 Muxes = 0
F5 Muxes = 9
F8 Muxes = 0
F7 Muxes = 0
Number of LUT signals with 4 loads = 1
Number of LUT signals with 3 loads = 0
Number of LUT signals with 2 loads = 34
Number of LUT signals with 1 load = 54
NGM Average fanout of LUT = 2.38
NGM Maximum fanout of LUT = 12
NGM Average fanin for LUT = 3.1373
Number of LUT symbols = 102