pblcd.syr

FPGA 基于PICOBLAZE内核的LCD显示程序,完整,XILINX

Release 8.1i - xst I.24
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 0.87 s | Elapsed : 0.00 / 1.00 s
 
--> Parameter xsthdpdir set to ./xst
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--> Reading design: PBLCD.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
     5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "PBLCD.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "PBLCD"
Output Format                      : NGC
Target Device                      : xc3s200-4-ft256

---- Source Options
Top Module Name                    : PBLCD
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
RTL Output                         : Yes
Global Optimization                : AllClockNets
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : PBLCD.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "D:/work/vhdl/PBLCD/kcpsm3.vhd" in Library work.
Architecture low_level_definition of Entity kcpsm3 is up to date.
Compiling vhdl file "D:/work/vhdl/PBLCD/LCD.VHD" in Library work.
Architecture low_level_definition of Entity lcd is up to date.
Compiling vhdl file "D:/work/vhdl/PBLCD/PBLCD.vhd" in Library work.
Architecture behavioral of Entity pblcd is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <PBLCD> (Architecture <behavioral>).
Entity <PBLCD> analyzed. Unit <PBLCD> generated.

Analyzing Entity <kcpsm3> (Architecture <low_level_definition>).
WARNING:Xst:2185 - "D:/work/vhdl/PBLCD/kcpsm3.vhd" line 289: Possible simulation mismatch on property <INIT> of instance <t_state_lut> set by attribute.
    Set user-defined property "INIT =  1" for instance <t_state_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "D:/work/vhdl/PBLCD/kcpsm3.vhd" line 332: Possible simulation mismatch on property <INIT> of instance <int_pulse_lut> set by attribute.
    Set user-defined property "INIT =  0080" for instance <int_pulse_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "D:/work/vhdl/PBLCD/kcpsm3.vhd" line 371: Possible simulation mismatch on property <INIT> of instance <int_update_lut> set by attribute.
    Set user-defined property "INIT =  EAAA" for instance <int_update_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "D:/work/vhdl/PBLCD/kcpsm3.vhd" line 381: Possible simulation mismatch on property <INIT> of instance <int_value_lut> set by attribute.
    Set user-defined property "INIT =  04" for instance <int_value_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "D:/work/vhdl/PBLCD/kcpsm3.vhd" line 403: Possible simulation mismatch on property <INIT> of instance <move_group_lut> set by attribute.
    Set user-defined property "INIT =  7400" for instance <move_group_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "D:/work/vhdl/PBLCD/kcpsm3.vhd" line 413: Possible simulation mismatch on property <INIT> of instance <condition_met_lut> set by attribute.
    Set user-defined property "INIT =  5A3C" for instance <condition_met_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "D:/work/vhdl/PBLCD/kcpsm3.vhd" line 423: Possible simulation mismatch on property <INIT> of instance <normal_count_lut> set by attribute.
    Set user-defined property "INIT =  2F" for instance <normal_count_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "D:/work/vhdl/PBLCD/kcpsm3.vhd" line 432: Possible simulation mismatch on property <INIT> of instance <call_type_lut> set by attribute.
    Set user-defined property "INIT =  1000" for instance <call_type_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "D:/work/vhdl/PBLCD/kcpsm3.vhd" line 442: Possible simulation mismatch on property <INIT> of instance <push_pop_lut> set by attribute.
    Set user-defined property "INIT =  5400" for instance <push_pop_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "D:/work/vhdl/PBLCD/kcpsm3.vhd" line 452: Possible simulation mismatch on property <INIT> of instance <valid_move_lut> set by attribute.
    Set user-defined property "INIT =  D" for instance <valid_move_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "D:/work/vhdl/PBLCD/kcpsm3.vhd" line 468: Possible simulation mismatch on property <INIT> of instance <flag_type_lut> set by attribute.
    Set user-defined property "INIT =  41FC" for instance <flag_type_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "D:/work/vhdl/PBLCD/kcpsm3.vhd" line 483: Possible simulation mismatch on property <INIT> of instance <flag_enable_lut> set by attribute.
    Set user-defined property "INIT =  8" for instance <flag_enable_lut> in unit <kcpsm3>.
WARNING:Xst:2185 - "D:/work/vhdl/PBLCD/kcpsm3.vhd" line 493: Possible simulation mismatch on property <INIT> of instance <low_zero_lut> set by attribute.