pblcd.par

来自「FPGA 基于PICOBLAZE内核的LCD显示程序,完整,XILINX」· PAR 代码 · 共 172 行

Release 8.1i par I.24
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

ZKF::  Sun Mar 18 11:40:36 2007

par -w -intstyle ise -ol std -t 1 PBLCD_map.ncd PBLCD.ncd PBLCD.pcf 


Constraints file: PBLCD.pcf.
Loading device for application Rf_Device from file '3s200.nph' in environment D:\Xilinx.
   "PBLCD" is an NCD, version 3.1, device xc3s200, package ft256, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
   -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
   internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For
   the fastest runtime, set the effort level to "std".  For best performance, set the effort level to "high". For a
   balance between the fastest runtime and best performance, set the effort level to "med".

Device speed data version:  "PRODUCTION 1.37 2005-11-04".


Device Utilization Summary:

   Number of BUFGMUXs                  1 out of 8      12%
   Number of External IOBs             8 out of 173     4%
      Number of LOCed IOBs             8 out of 8     100%

   Number of RAMB16s                   1 out of 12      8%
   Number of Slices                   91 out of 1920    4%
      Number of SLICEMs               34 out of 960     3%



Overall effort level (-ol):   Standard 
Placer effort level (-pl):    High 
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard 


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:989934) REAL time: 8 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 8 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 12 secs 

Phase 4.8
...................................................
..
.........................................................................
...
..
.....................
Phase 4.8 (Checksum:9b3237) REAL time: 14 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 14 secs 

Phase 6.18
Phase 6.18 (Checksum:39386fa) REAL time: 15 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 15 secs 

Writing design to file PBLCD.ncd


Total REAL time to Placer completion: 15 secs 
Total CPU time to Placer completion: 12 secs 

Starting Router

Phase 1: 868 unrouted;       REAL time: 16 secs 

Phase 2: 782 unrouted;       REAL time: 16 secs 

Phase 3: 203 unrouted;       REAL time: 16 secs 

Phase 4: 203 unrouted; (19088)      REAL time: 16 secs 

Phase 5: 204 unrouted; (0)      REAL time: 17 secs 

Phase 6: 0 unrouted; (0)      REAL time: 17 secs 

Phase 7: 0 unrouted; (0)      REAL time: 18 secs 


Total REAL time to Router completion: 18 secs 
Total CPU time to Router completion: 14 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|           clk_BUFGP |      BUFGMUX0| No   |   77 |  0.041     |  1.051      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.


   The Delay Summary Report


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.214
   The MAXIMUM PIN DELAY IS:                               3.847
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   3.101

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
         323         443         121          11           0           0

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

------------------------------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic  | Absolute   |Number of  
                                            |            |            | Levels | Slack      |errors     
------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net clk | N/A        | 9.226ns    | 4      | N/A        | N/A       
  _BUFGP                                    |            |            |        |            |           
------------------------------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 19 secs 
Total CPU time to PAR completion: 15 secs 

Peak Memory Usage:  112 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file PBLCD.ncd



PAR done!