pblcd.twr
来自「FPGA 基于PICOBLAZE内核的LCD显示程序,完整,XILINX」· TWR 代码 · 共 57 行
TWR
57 行
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Release 8.1i Trace I.24
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
D:\Xilinx\bin\nt\trce.exe -ise PBLCD.ise -intstyle ise -e 3 -l 3 -s 4 -xml
PBLCD PBLCD.ncd -o PBLCD.twr PBLCD.pcf
Design file: pblcd.ncd
Physical constraint file: pblcd.pcf
Device,speed: xc3s200,-4 (PRODUCTION 1.37 2005-11-04)
Report level: error report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Clock clk to Pad
------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
lcd_d<4> | 7.360(R)|clk_BUFGP | 0.000|
lcd_d<5> | 7.360(R)|clk_BUFGP | 0.000|
lcd_d<6> | 7.360(R)|clk_BUFGP | 0.000|
lcd_d<7> | 7.360(R)|clk_BUFGP | 0.000|
lcd_e | 7.359(R)|clk_BUFGP | 0.000|
lcd_rs | 7.359(R)|clk_BUFGP | 0.000|
lcd_rw | 7.359(R)|clk_BUFGP | 0.000|
------------+------------+------------------+--------+
Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk | 9.226| | | |
---------------+---------+---------+---------+---------+
Analysis completed Sun Mar 18 11:41:05 2007
--------------------------------------------------------------------------------
Peak Memory Usage: 103 MB
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