arminstrs.txt

ARM平台详细介绍

decode the SWI number and execute the appropriate routines).


55..99..  CCoo--pprroocceessssoorr ddaattaa ooppeerraattiioonnss


xxxxxxxx11111100 oooooooonnnnnnnn ddddddddpppppppp qqqqqq00mmmmmmmm


Typical Assembler Syntax:


       CCDDPP pp,, oo,, CCRRdd,, CCRRnn,, CCRRmm,, qq
       CCDDPP pp,, oo,, CCRRdd,, CCRRnn,, CCRRmm


This  instruction  is  passed  on  to co-processor p, telling it to perform
operation o, on co-processor registers CRn and CRm, and  place  the  result
into Crd.

qqq may supply additional information about the operation concerned.

The  exact  meaning of these instructions depends on the particular co-pro-
cessor in use; The above is only a recommended  usage  for  the  bits  (and









                                    -18-


indeed the FPA doesn't conform to it). The only part which is obligatory is
that pppp must be the coprocessor number: the coprocessor designer is  free
to allocate oooo, nnnn, dddd, qqq and mmmm as desired.

If  the  coprocessor  uses the bits in a different way than the recommended
one, assembler macros will probably be needed to translate the  instruction
syntax  that  makes  sense  to people into the correct CDP instruction. For
commonly used coprocessors such as the FPA, many assemblers have the  extra
mnemonics  built  in  and  do this translation automatically. (For example,
assembling MUFEZ F0,F1,#10 as its equivalent CDP 1,1,CR0,CR9,CR15,3.)

Currently defined co-processor numbers include:

                       1 and 2   Floating Point unit
                       15        Cache Controller


If a call to a coprocessor is made and the  coprocessor  does  not  respond
(normally  becuase  it  isn't  there!), the undefined instruction vector is
called (exactly as for one of the undefined instructions given later). This
is used to transparently provide FP support on machines without an FPA.

These instructions take 1S + bI cycles to execute, where b is the number of
cycles that the coprocessor causes the ARM to busy-wait before  it  accepts
the instruction: again, this is under the coprocessor's control.


55..1100..  CCoo--pprroocceessssoorr ddaattaa ttrraannssffeerr aanndd rreeggiisstteerr ttrraannssffeerrss


xxxxxxxx111100PP UUNNWWLLnnnnnnnn DDDDDDDDpppppppp oooooooooooooooo LLDDCC//SSTTCC
xxxxxxxx11111100 ooooooLLNNNNNNNN ddddddddpppppppp qqqqqq11MMMMMMMM MMRRCC//MMCCRR


Again these depend on the particular co-processor p in use.

N  and  D  signify co-processor register numbers, n and d are ARM processor
numbers. o is the co-processor operation  to  use.  M  signifies  bits  the
coprocessor is free to use as it wants.

The  first form, denotes LDC if L=1, STC otherwise. The instruction behaves
like LDR or STR respectively, in each case with an immediate  offset,  with
the following exceptions.

+o    The offset is 4*(oooooooo), not a general 12-bit constant.

+o    If  P=0  (post-indexing) is specified, W must be 1, and W being 1 just
     indicates that writeback is  required,  not  that  the  memory  system
     should  be  told  that this is a user mode transfer. Instructions with
     P=0 and W=0 are reserved for future expansion.

+o    One or more coprocessor registers are loaded or stored. The  coproces-
     sor determines how many and which registers are to be loaded or stored
     from the DDDD and N bits: all the ARM does is transfer a  word  to  or









                                    -19-


     from  the  indicated  address,  then  another to or from the indicated
     address + 4, then one to or from the  indicated  address  +  8,  etc.,
     until the coprocessor tells it to stop.

+o    By  convention,  DDDD denotes the (first) coprocessor register to load
     or store and N denotes the length in some way, with N=1  indicating  a
     "long" form. Coprocessor designers are free to ignore this...

+o    The assembler syntax is along the lines of:


     LLDDCC    pp,,CCRRdd,,[[RRnn,,##2200]]   ;;sshhoorrtt ffoorrmm ((NN==00)),, pprree--iinnddeexxeedd
     SSTTCCLL   pp,,CCRRdd,,[[RRnn,,##--3322]]!! ;;lloonngg ffoorrmm ((NN==11)),, pprree--iinnddeexxeedd wwiitthh wwrriitteebbaacckk
     LLDDCCNNEELL pp,,CCRRdd,,[[RRnn]],,##--110000 ;;lloonngg ffoorrmm ((NN==11)),, ppoosstt--iinnddeexxeedd


The  second  form  denotes,  MRC,  if  L=1, MCR otherwise.  MRC transfers a
coprocessor register to an ARM register, MCR the other way around (the let-
ters may seem the wrong way around, but remember that destinations are usu-
ally written on the left in ARM assembler).

MCR transfers the contents of ARM  register  Rd  to  the  coprocessor.  The
coprocessor  is free to do whatever it wants with it based on the values of
the ooo, dddd, qqq and MMMM fields, though as usual there is  a  "standard"
interpretation:  write it to coprocessor register CRN, using operation ooo,
with possible additional control provided by CRM  and  qqq.  The  assembler
syntax is:


       MMCCRR   pp,,oo,,RRdd,,CCRRNN,,CCRRMM,,qq


Rd should not be R15 for an MCR instruction.

MRC  transfers a single word from the coprocessor and puts it in ARM regis-
ter Rd. The coprocessor is free to generate this word in any way  it  likes
using  the same fields as for MCR, with the standard interpretation that it
comes from CRN using operation ooo, with possible additional  control  pro-
vided by CRM and qqq. The assembler syntax is:


       MMRRCC   pp,,oo,,RRdd,,CCRRNN,,CCRRMM,,qq


If Rd is R15 for an MRC instruction, the top 4 bits of the word transferred
are used to set the flags; the remaining 28 bits are  discarded.  (This  is
the mechanism used e.g. by floating point comparison instructions.)

LDC  and  STC  take  (n-1)S + 2N + bI cycles to execute, MRC takes 1S+bI+1C
cycles, and MCR takes 1S + (b+1)I + 1C cycles, where b  is  the  number  of
cycles  that  the coprocessor causes the ARM to busy-wait before it accepts
the instruction: again, this is under the coprocessor's control, and  n  is
the number of words being transferred (Note this is under the coprocessor's
control, not the ARM's)









                                    -20-


55..1111..  SSiinnggllee DDaattaa SSwwaapp ((AARRMM 33 aanndd llaatteerr iinncclluuddiinngg AARRMM 22aaSS))


xxxxxxxx00000011 00BB0000nnnnnnnn dddddddd00000000 11000011mmmmmmmm


Typical Assembler Syntax:


       SSWWPP RRdd,, RRmm,, [[RRnn]]


These instructions load a word of memory (address given by register Rn)  to
a register Rd and store the contents of register Rm to the same address. Rm
and Rd may be the same register, in which case the contents of this  regis-
ter  and  of the memory location are swapped. The load and store operations
are locked together by setting the LOCK pin high during  the  operation  to
indicate  to  the  memory  manager  that they should be allowed to complete
without interruption.

If the B bit is set, then a byte of memory is transferred, otherwise a word
is transferred.

None of Rd, Rn, and Rm may be R15.

This instruction takes 1S + 2N + 1I cycles to execute.


55..1122..  SSttaattuuss RReeggiisstteerr ttrraannssffeerr ((AARRMM 66 aanndd llaatteerr))


xxxxxxxx00000011 00ss1100aaaaaaaa 1111111100000000 00000000mmmmmmmm  MMSSRR  RReeggiisstteerr ffoorrmm
xxxxxxxx00001111 00ss1100aaaaaaaa 11111111rrrrrrrr bbbbbbbbbbbbbbbb  MMSSRR  IImmmmeeddiiaattee ffoorrmm
xxxxxxxx00000011 00ss000011111111 dddddddd00000000 0000000000000000  MMRRSS


Typical Assembler Syntax:


       MMSSRR   SSPPSSRR__aallll,, RRmm          ;;aaaaaaaa == 11000011
       MMSSRR   CCPPSSRR__ffllgg,, ##&&FF00000000000000  ;;aaaaaaaa == 11000000
       MMSSRRNNEE CCPPSSRR__ccttll,, RRmm          ;;aaaaaaaa == 00000011
       MMRRSS   RRdd,, CCPPSSRR


The  s  bit, when set means access the SPSR of the current privileged mode,
rather than the CPSR. This bit must only be set when executing the  command
in a privileged mode.

MSR is used for transfering a register or constant to a status register.

The aaaa bits can take the following values:











                                    -21-


 Value   Meaning

 0001    Set the control bits of the PSR concerned.
 1000    Set the flag bits of the PSR concerned.
 1001    Set the control and flag bits of the PSR concerned (i.e. all the
         bits at present).

Other values of aaaa are reserved for future expansion.

In the register form, the source register is Rm. In the immediate form, the
source is #b, ROR #2r.

R15 should not be specified as the source register of an MRS instruction.

MRS is used for transfering processor status to a register.

The d bits store the destination register number; Rd must not be R15.

N.B. The instruction encodings correspond to the data  processing  instruc-
tions with opcodes 10xx (i.e. the test instructions) and the S bit clear.

These instruction always execute in 1-S cycle.


55..1133..  UUnnddeeffiinneedd iinnssttrruuccttiioonnss


xxxxxxxx00000011 yyyyyyyyyyyyyyyy yyyyyyyyyyyyyyyy 11yyyy11yyyyyyyy AARRMM 22 oonnllyy
xxxxxxxx001111yy yyyyyyyyyyyyyyyy yyyyyyyyyyyyyyyy yyyyyy11yyyyyyyy


These  instructions  are  currently undefined. On encountering an undefined
instruction, the ARM switches to SVC mode (on ARM 3  and  below)  or  Undef
mode  (on  ARM  6  and  above),  puts the old value of R15 into R14_SVC (or
R14_UND) and jumps to location, where it expects to find code to decode the
undefined instruction and behave accordingly.

Notes:

+o    These  instructions  are  documented as "undefined" because they enter
     the undefined instruction processor trap in this way. Plenty of  other
     instructions  are undefined in the looser sense that nothing says what
     they do. For instance, bit patterns of the form:

                              xxxx0000 01xxxxxx xxxxxxxx 1001xxxx

     are related to data processing instructions, multiplies,  long  multi-
     plies and SWPs, but are none of these because:

*    Data processing instructions with bit 25 = 0 and bit 4 = 1 have regis-
     ter controlled shifts, and so must have bit 7 = 0.

*    Multiply instructions have bits 23:22 = 00.










                                    -22-


*    Long multiply instructions have bits 23:22 = 1U.

*    SWPs have bit 24 = 1.
What these instructions do simply isn't defined, whereas  the  ones  listed
above  are  actually  ddeeffiinneedd  to  enter the undefined instruction trap, at
least until some future use is found for them.

+o    Note that the "ARM2 only" undefined instructions  include  those  that
     became SWP instructions on ARM3/ARM2as and later.


66..  CCrreeddiittss

This document was originally written by Robin Watts, with considerable con-
sultation with Steven Singer. It was then later updated by  Mark  Smith  to
include more information on ARMs later than 2.

David  Seal  provided a huge list of corrections and amendments, and unwit-
tingly provided the basis for  the  timing  information  in  a  posting  to
usenet.

Various  corrections were also submitted/posted by Olly Betts, Clive Jones,
Alain Noullez, John Veness, Sverker Wiberg and Mark Wooding.

Thanks to everyone that helped (and if I have missed you here,  please  let
me know.)

JJuusstt  bbeeccaauussee  II  hhaavvee  iinncclluuddeedd ppeeoopplleess aaddddrreesssseess hheerree,, pplleeaassee ddoo nnoott ttaakkee
tthhiiss aass aann iinnvviittaattiioonn ttoo mmaaiill tthheemm aannyy qquueessttiioonnss yyoouu mmaayy hhaavvee!!


              Olly Betts       [e-mail]
              Paul Hankin      [e-mail]
              Robert Harley    [e-mail]
              Clive Jones      [e-mail]
              Alain Noullez    [e-mail]
              David Seal       <address withheld by request>
              Steven Singer    [e-mail]
              Mark Smith       [e-mail]
              John Veness      [e-mail]
              Robin Watts      [e-mail]
              Sverker Wiberg   [e-mail]
              Mark Wooding     [e-mail]


For those not on the internet, messages can be sent by snail mail to:


                          Robin Watts
                          St Catherines College,
                          Oxford,
                          OX1 3UJ