arminstrs.txt

ARM平台详细介绍

                                    -12-


                   &8000000 -- &1FFFFFFF     1S + 15I
                  &20000000 -- &FFFFFFFF     1S + 16I


These multiplication timings don't apply  to  ARM7DM.  ARM7DM  timings  are
given by the following table.

                                         MLA/
              Range of Rs        MUL     SMULL   SMLAL   UMULL   UMLAL

               &0 -- &FF         1S+1I   1S+2I   1S+3I   1S+2I   1S+3I
             &100 -- &FFFF       1S+2I   1S+3I   1S+4I   1S+3I   1S+4I
           &10000 -- &FFFFFF     1S+3I   1S+4I   1S+5I   1S+4I   1S+5I
         &1000000 -- &FEFFFFFF   1S+4I   1S+5I   1S+6I   1S+5I   1S+6I
        &FF000000 -- &FFFEFFFF   1S+3I   1S+4I   1S+5I   1S+5I   1S+6I
        &FFFF0000 -- &FFFFFEFF   1S+2I   1S+3I   1S+4I   1S+5I   1S+6I
        &FFFFFF00 -- &FFFFFFFF   1S+1I   1S+2I   1S+3I   1S+5I   1S+6I



55..55..  LLoonngg MMuullttiipplliiccaattiioonn ((AARRMM77DDMM))


xxxxxxxx00000000 11UUAASShhhhhhhh llllllllssssssss 11000011mmmmmmmm


Typical Assembler Syntax:


        UUMMUULLLL  RRll,,RRhh,,RRmm,,RRss
        UUMMLLAALL  RRll,,RRhh,,RRmm,,RRss
        SSMMUULLLL  RRll,,RRhh,,RRmm,,RRss
        SSMMLLAALL  RRll,,RRhh,,RRmm,,RRss


These  instructions  multiply the values of registers Rm and Rs to obtain a
64-bit product.

When the U bit is clear the multiply is unsigned (UMULL or  UMLAL),  other-
wise  signed  (SMULL, SMLAL).  When the A bit is clear the result is stored
with its least significant half in Rl and its most significant half in  Rh.
When A is set, the result is instead added to the contents of Rh,Rl.

The  program counter, R15 should not be used.  Rh, Rl and Rm should be dif-
ferent.

If the S bit is set, the N and Z flags are set on the 64-bit result, C  and
V are undefined.

Timings for these can be found above in the multiplication section.













                                    -13-


55..66..  SSiinnggllee DDaattaa TTrraannssffeerr


xxxxxxxx001100PP UUBBWWLLnnnnnnnn ddddddddoooooooo oooooooooooooooo  IImmmmeeddiiaattee ffoorrmm
xxxxxxxx001111PP UUBBWWLLnnnnnnnn ddddddddcccccccc cctttt00mmmmmmmm  RReeggiisstteerr ffoorrmm


Typical Assembler Syntax:


        LLDDRR  RRdd,, [[RRnn,, RRmm,, AASSLL##11]]!!
        SSTTRR  RRdd,, [[RRnn]],,##22
        LLDDRRTT RRdd,, [[RRnn]]
        LLDDRRBB RRdd,, [[RRnn]]


These  instructions  load/store  a  word  of memory from/to a register. The
first register used in specifying the address is termed the base  register.

If the L bit is set, then a load is performed. If not, a store.

If  the  P bit is set, then Pre-indexed addressing is used, otherwise post-
indexed addressing is used.

If the U bit is set, then the offset given is added to the base register --
otherwise it is subtracted.

If the B bit is set, then a byte of memory is transferred, otherwise a word
is transferred. This is signified to assemblers by postfixing the  mnemonic
stub with a `B'.

The interpretation of the W bit depends on the addressing mode used:

+o    For pre-indexed addressing, W being set forces the writing back of the
     final address used for the address translation into the base register.
     (i.e.   A  side effect of the transfer is Rn := Rn +/- offset. This is
     signified to assemblers by postfixing the instruction with !.)

+o    For post-indexed addressing, the address is always written  back,  and
     the  bit  being  set  indicates  that an address translation should be
     forced before the transfer takes place. This is  signified  to  assme-
     blers by postfixing the mnemonic stub with `T'.

An  address translation causes the chip to tell the memory system that this
is a user mode transfer, regardless of whether the chip is in a  user  mode
or  a  privileged mode at the time. This is useful e.g. when writing emula-
tors: suppose for instance  that  a  user  mode  program  executes  an  STF
instruction to an area of memory that may not be written by user mode code.
If this is executed by an FPA, it will abort. If it is executed by the FPE,
it  should also abort. But the FPE runs in a privileged mode, so if it were
to use normal stores, they wouldn't abort. To make aborts work properly, it
instead  uses  normal  stores  if it was called from a privileged mode, but
STRTs if it was called from a user mode.










                                    -14-


If the immediate form of the instruction is  used,  the  o  field  gives  a
12-bit  offset. If the register form is used, then it is decoded as for the
data processing instructions, with the restriction that shifts by  register
amounts are not allowed.

If R15 is used as Rd, the PSR is not modified. The PC should not be used in
Op2.

Other restrictions:

+o    Don't use writeback or post-indexing when the base register is the PC.

+o    Don't use the PC as Rd for an LDRB or STRB.

+o    When  using post-indexing with a register offset, don't make Rn and Rm
     the same register (doing so makes recovery from aborts impossible).

A load takes 1S + 1N + 1I + (1S + 1N if PC changed)  cycles,  and  a  store
takes 2N cycles.


55..77..  BBlloocckk DDaattaa TTrraannssffeerr


xxxxxxxx110000PP UUSSWWLLnnnnnnnn llllllllllllllll llllllllllllllll


Typical Assembler Syntax:


        LLDDMMFFDD   RRnn!!,, {{RR00--RR44,, RR88,, RR1122}}
        SSTTMMEEQQIIAA RRnn,,   {{RR00--RR33}}
        SSTTMMIIBB   RRnn,,   {{RR00--RR33}}^^


These  instructions  are  used  to  load/store  large  numbers of registers
from/to memory at a time. The memory addresses used are  either  increasing
or  decreasing  in  memory from a value held in a base register, Rn, (which
may itself be stored), and the final address can be written back  into  the
base.  These  instructions  are  ideal  for  implementing stacks, and stor-
ing/restoring the contents of registers on entry/exit from a subroutine.

The U bit indicates whether the address will be modified by +4 (set), or -4
(clear) for each register.

The W bit always indicates writeback.

If set, the L bit indicates a load operation should be performed. If clear,
a save.

The P bit is used indicate whether to increment/decrement the  base  before
or after each load/store (see the table below).











                                    -15-


Bit l is set if Rl is to be loaded/stored by this operation.

Assemblers  typically  follow  the mnemonic stub with a condition code, and
then a two letter code to indicate the settings of the U and W bits.

            Stub   Meaning                               P   U

            DA     Decrement Rn After each store/load    0   0
            DB     Decrement Rn Before each store/load   1   0
            IA     Increment Rn After each store/load    0   1
            IB     Increment Rn Before each store/load   1   1


Synonyms for these exist which are clearer when implementing stacks:

                       Stub   Meaning

                       EA     Empty Ascending stack
                       ED     Empty Decending stack
                       FA     Full Ascending stack
                       FD     Full Decending stack


In an empty stack, the stack pointer points to the next empty position.  In
a full one the stack pointer points to the topmost full position. Ascending
stacks grow towards high locations, and descending stacks grow towards  low
locations.

The  registers are always stored so that the lowest numbered register is at
the lowest address in memory. This can affect stacking and unstacking code.
For  instance,  if  I want to push R1-R4 on to a stack, then load them back
two at a time, to get them back to the same registers, I need to  do  some-
thing like:


   SSTTMMFFDD RR1133!!,,{{RR11,,RR22,,RR33,,RR44}}  ;;PPuuttss RR11 llooww iinn mmeemmoorryy,, ii..ee.. aatt eenndd ooff ssttaacckk
   LLDDMMFFDD RR1133!!,,{{RR11,,RR22}}
   LLDDMMFFDD RR1133!!,,{{RR33,,RR44}}


for a descending stack, but something like:


   SSTTMMFFAA RR1133!!,,{{RR11,,RR22,,RR33,,RR44}}  ;;PPuuttss RR44 hhiigghh iinn mmeemmoorryy,, ii..ee.. aatt eenndd ooff ssttaacckk
   LLDDMMFFAA RR1133!!,,{{RR33,,RR44}}
   LLDDMMFFAA RR1133!!,,{{RR11,,RR22}}


for an ascending stack.

The codes are synonyms as follows:

                            Code   Load   Store










                                    -16-



                             EA     DB     IA
                             ED     IB     DA
                             FA     DA     IB
                             FD     IA     DB

The  S  bit  controls two special functions, both of which are indicated to
the assembler by putting "^" at the end of the instruction:

+o    If the S bit is set, the instruction is LDM and R15 is in the register
     list, then:

*    In 26-bit privileged modes, all 32 bits of R15 will be loaded.

*    In 26-bit user mode, the 4 flags and 24 PC bits of R15 will be loaded.
     Bits 27, 26, 1 and 0 of the loaded value will be ignored.

*    In 32-bit modes, all 32 bits of R15 will be loaded, though  note  that
     the  two  bottom bits are always zero, so any ones loaded to them will
     be ignored. In addition, the SPSR of the current mode will  be  trans-
     ferred  to  the CPSR; since user mode does not have an SPSR, this type
     of instruction should not be used in 32-bit user mode.

+o    If the S bit is set and either the instruction is STM or R15 is not in
     the  register  list,  then the user mode registers will be transferred
     rather than those for the  current  mode.  This  type  of  instruction
     should not be used in user mode.

Special cases occur when the base register is used in the list of registers
to be transferred.

+o    The base register can always be loaded without any problems.  However,
     don't  specify  writeback  if the base register is being loaded -- you
     can't end up with both a written-back value and a loaded value in  the
     base register!

+o    The  base  register  can  be  stored  with no complications as long as
     writeback is not used.

+o    Storing a list of registers including the base register  using  write-
     back  will  write  the  value of the base register before writeback to
     memory only if the base register is the first in the list.  Otherwise,
     the value which is used is not defined.

Further  special  cases occur if the program counter is present in the list
of registers to load and save.

+o    The PSR is always saved with the PC (in 26 bit modes) (and the PC will
     always  be  12  bytes  further  on,  rather  than  the usual 8 (in all
     modes)).

+o    On a load, only the bits of the PSR that are alterable in the  current
     mode can be affected, and then only if the S bit is set.










                                    -17-


The PC should not be used as the base register.

A block data load, takes nS + 1N + 1I + (1S + 1N if PC changed) cycles, and
a block data store takes (n-1)S + 2N cycles, where "n"  is  the  number  of
words being transferred.


55..88..  SSooffttwwaarree iinntteerrrruupptt


xxxxxxxx11111111 yyyyyyyyyyyyyyyy yyyyyyyyyyyyyyyy yyyyyyyyyyyyyyyy


Typical Assembler Syntax:


       SSWWII   ""OOSS__WWrriitteeII""
       SSWWIINNEE &&440000CC00


On encountering a software interrupt, the ARM switches into SVC mode, saves
the current value of R15 into R14_SVC, and jumps to location 8  in  memory,
where it assumes it will find a SWI handling routine to decode the lower 24
bits of the SWI just executed, and do whatever  the  SWI  number  concerned
means on that particular operating system.

An  operating  system written on the ARM will typically use SWIs to provide
miscellaneous routines for programmers.

A SWI takes 2S + 1N cycles to execute (plus whatever time  is  required  to