arminstrs.txt

ARM平台详细介绍

55..11..  CCoonnddiittiioonn CCooddee

The top nibble of every instruction is a condition code,  so  every  single
ARM instruction can be run conditionally.


                                    Cond
Instruction Bitmap                   No  Cond Code            Executes if

00000000xxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx  0   EQ(Equal)            Z
00000011xxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx  1   NE(Not Equal)        ~Z
00001100xxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx  2   CS(Carry Set)        C
00001111xxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx  3   CC(Carry Clear)      ~C

00110000xxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx  4   MI(MInus)            N
00110011xxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx  5   PL(PLus)             ~N
00111100xxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx  6   VS(oVerflow Set)     V
00111111xxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx  7   VC(oVerflow Clear)   ~V

11000000xxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx  8   HI(HIgher)           C and ~Z
11000011xxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx  9   LS(Lower or Same)    ~C or Z
11001100xxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx  A   GE(Greater or equal) N = V
11001111xxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx  B   LT(Less Than)        N = ~V

11110000xxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx  C   GT(Greater Than)     (N = V) and ~Z










                                    -7-


11110011xxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx  D   LE(Less or equal)    (N = ~V) or Z
11111100xxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx  E   AL(Always)           True
11111111xxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx  F   NV(Never)            False


In  most  assemblers,  the condition code is inserted immediately after the
mnemonic stub; omitting a condition code defaults to AL being used.

HS (Higher or Same) and LO (LOwer) can be used as synonyms for  CS  and  CC
(respectively) in some assemblers.

The  conditions  GT, GE, LT, LE refer to signed comparisons whereas HS, HI,
LS, LO refer to unsigned.

EORing a condition code with 1 gives the opposite condition code.

NB: ARM have deprecated the use of the NV condition code  --  you  are  now
supposed  to  use MOV R0,R0 as a noop rather than MOVNV R0,R0 as was previ-
ously recommended. Future processors may have the NV condition code  reused
to do other things.

Instructions with false conditions execute in 1S cycle, and no time penalty
is incurred by making an instruction conditional.


55..22..  DDaattaa PPrroocceessssiinngg IInnssttrruuccttiioonnss


xxxxxxxx000000aa aaaaaaSSnnnnnnnn ddddddddcccccccc ccttttttmmmmmmmm  RReeggiisstteerr ffoorrmm
xxxxxxxx000011aa aaaaaaSSnnnnnnnn ddddddddrrrrrrrr bbbbbbbbbbbbbbbb  IImmmmeeddiiaattee ffoorrmm


Typical Assembler Syntax:


        MMOOVV    RRdd,, ##00
        AADDDDEEQQSS RRdd,, RRnn,, RRmm,, AASSLL RRcc
        AANNDDEEQQ  RRdd,, RRnn,, RRmm
        TTEEQQPP   PPnn,, ##&&8800000000000000
        CCMMPP    RRnn,, RRmm


Combine contents of Rn with Op2, under operation a, placing the results  in
Rd.

If  the  register  form  is  used, then Op2 is set to be the contents of Rm
shifted according to t as below.  If the immediate form is used, then Op2 =
#b, ROR #2r.

       t    Assembler               Interpretation

      000   LSL #c                  Logical Shift Left
      001   LSL Rc                  Logical Shift Left










                                    -8-


      010   LSR #c    for c != 0    Logical Shift Right
            LSR #32   for c  = 0
      011   LSR Rc                  Logical Shift Right
      100   ASR #c    for c != 0    Arithmetic Shift Right
            ASR #32   for c  = 0
      101   ASR Rc                  Arithmetic Shift Right
      110   ROR #c    for c != 0    Rotate Right.
            RRX       for c  = 0    Rotate Right one bit with extend.
      111   ROR Rc                  Rotate Right


In  the register form, Rc is signified by bits 8-11; bit 7 must be clear if
Rc is used. (If you code a 1 instead, you'll get a multiply, a SWP or some-
thing unallocated instead of a data processing instruction.)

Also,  only  the  bottom byte of Rc is used -- If Rc = 256, then the shifts
will be by zero.

"MOV[S] Ra,Rb,RLX" can be done by ADC[S] Ra,Rb,Rb, with RLX meaning  Rotate
Left one bit with extend.

Most  assemblers  allow ASL to be used as a synonym for LSL. Since opinions
differ on what an arithmetic left shift is, LSL is the preferred term.

By setting the S bit in a MOV, MVN or logical instruction, (in  either  the
register  or  immediate  form)  the  carry  flag  is set to be the last bit
shifted out.

If no shift is done, the carry flag will be unaffected.

If there is a choice of forms for an immediate (e.g.  #1  could  be  repre-
sented  as  1  ROR  #0, 4 ROR #2, 16 ROR #4 or 64 ROR #6), the assembler is
expected to use the one involving a zero rotation, if  available.  So  MOVS
Rn,#const  will  leave  the carry flag unaffected if 0 <= const <= 255, but
will change it otherwise.


     aaaa   Assembler   Meaning                P-Code

     0000   AND         Boolean And            Rd = Rn AND Op2
     0001   EOR         Boolean Eor            Rd = Rn EOR Op2
     0010   SUB         Subtract               Rd = Rn  -  Op2
     0011   RSB         Reverse Subtract       Rd = Op2 -  Rn
     0100   ADD         Addition               Rd = Rn  +  Op2
     0101   ADC         Add with Carry         Rd = Rn  +  Op2 + C
     0110   SBC         Subtract with carry    Rd = Rn  -  Op2 - (1-C)
     0111   RSC         Reverse sub w/carry    Rd = Op2 -  Rn  - (1-C)
     1000   TST         Test bit               Rn AND Op2
     1001   TEQ         Test equality          Rn EOR Op2
     1010   CMP         Compare                Rn  -  Op2
     1011   CMN         Compare Negative       Rn  + Op2
     1100   ORR         Boolean Or             Rd = Rn OR  Op2
     1101   MOV         Move value             Rd =        Op2










                                    -9-


     1110   BIC         Bit clear              Rd = Rn AND NOT Op2
     1111   MVN         Move Not               Rd =    NOT Op2

Note that MVN and CMN are not as related as they  first  appear;  MVN  uses
straight  bitwise  negation,  setting  Rn to the 1's complement of Op2. CMN
compares Rn with the 2's complement of Op2.

These instructions fall broadly into 4 subsets:

MOV, MVN
   Rn is ignored, and should be 0000. If the S bit is set, N and Z are  set
   on  the  result, and if the shifter is used, C is set to be the last bit
   shifted out. V is unaffected.

CMN, CMP, TEQ, TST
   Rd is not set by the instruction, and should be 0000. The S bit must  be
   set  (most  assemblers  do  this  automatically;  if it weren't set, the
   instruction would be MRS, MSR, or an unallocated one.)

   The arithmetic operations (CMN, CMP) set N, Z on result,  and  C  and  V
   from the ALU.

   The  logical operations (TEQ, TST) set N and Z on the result, C from the
   shifter if it is used (in which case it becomes  the  last  bit  shifted
   out), and V is unaffected.

   As a special case (for ARMs >= 6, this only applies to 26 bit code), the
   dddd field being 1111 causes flags (in user mode), or the entire 26  bit
   PSR  (in  privileged modes) to be set from the corresponding bits of the
   result. This is indicated by a P suffix  to  the  instruction  --  CMNP,
   CMPP,  TEQP,  TSTP.  This  is most commonly used to change mode via TEQP
   PC,#(new mode number). In 32 bit modes, MSR should be used  instead  (as
   TEQP etc will not work).

ADC, ADD, RSB, RSC, SBC, SUB
   If the S bit is set, then N and Z are set on result, and C and V are set
   from the ALU.

AND, BIC, EOR, ORR
   If the S bit is set, then N and Z are set on result, C is set  from  the
   shifter  if used (in which case it becomes the last bit shifted out) and
   V is unaffected.

ADD and SUB can be used to make registers point to data in a position inde-
pendent way, eg. ADD R0,PC,#24. This is so useful that some assemblers have
a special directive called ADR which generates the appropriate ADD  or  SUB
automatically.  (ADR  R0,  fred typically puts the address of fred into R0,
assuming fred is within range).

In 26-bit modes, special cases occur when R15 is one of the registers being
used:

+o    If  Rn  =  R15 then the value used is R15 with all the PSR bits masked
     out.









                                    -10-


+o    If Op2 involves R15, then all 32 bits are used.

In 32-bit modes, all the bits of R15 are used.

In 26-bit modes, if Rd = R15 then:

+o    If the S bit is not set, only the 24 bits of the PC are set.

+o    If the S bit is set, both the PC and PSR are overwritten  (though  the
     Mode,  I  and  F  bits will not be altered unless we are in a non-user
     mode.)

For 32-bit modes, if Rd=15, all the bits of the  PC  will  be  overwritten,
except the two least significant bits, which are always zero.  If the S bit
is not set, that is all that happens; if the S bit is set, the SPSR for the
current  mode is copied to the CPSR. You should not execute a data process-
ing instruction with the PC as destination and the S bit set in 32-bit user
mode,  since  user mode does not have an SPSR. (By the way, you won't break
the processor by doing so -- it's just that the results of doing so  aren't
defined, and may differ between processors.)

These instructions take the following number of cycles to execute: 1S + (1S
if register controlled shift used) + (1S + 1N if PC changed)


55..33..  BBrraanncchh IInnssttrruuccttiioonnss


xxxxxxxx110011LL oooooooooooooooo oooooooooooooooo oooooooooooooooo


Typical Assembler Syntax:


        BBEEQQ  aaddddrreessss
        BBLLNNEE ssuubbrroouuttiinnee


These instructions are used to force a jump to a new address, given  as  an
offset in words from the value of the PC as this instruction is executed.

Due to the pipeline, the PC is always 2 instructions (8 bytes) ahead of the
address at which this instruction was stored, so a  branch  with  offset  =
(sign extended version of bits 0-23):

            destination address = current address + 8 + (4 * offset)

In 26-bit modes, the top 6 bits of the destination address are cleared.

If  the  L flag is set, then the current contents of PC are copied into R14
before the branch is taken. Thus R14 holds the address of  the  instruction
after the branch, and the called routine can return with MOV PC,R14.











                                    -11-


In  26-bit modes, using MOVS PC,R14, to return from a branch with link, the
PSR flags can be restored automatically on return. The  behaviour  of  MOVS
PC,R14  is  different in 32-bit modes, and only suitable for return from an
exception.

Both branch and branch with links, take 2S+1N cycles to execute.


55..44..  MMuullttiipplliiccaattiioonn


xxxxxxxx00000000 0000AASSdddddddd nnnnnnnnssssssss 11000011mmmmmmmm


Typical Assembler Syntax:


        MMUULLEEQQSS RRdd,, RRmm,, RRss
        MMLLAA    RRdd,, RRmm,, RRss,, RRnn


These instructions multiply the values of 2 registers, and optionally add a
third, placing the result in another register.

If  the  S  bit is set, the N and Z flags are set on the result, C is unde-
fined, and V is unaffected.

If the A bit is set, then the effect of the operation is Rd =  Rm.Rs  +  Rn
otherwise, Rd = Rm.Rs.

The  destination register shall not be the same as the operand register Rm.
R15 shall not be used as an operand or as the destination register.

These instructions take 1S + 16I cycles to execute in the worst  case,  and
may  be  less  depending on arguement values. The exact time depends on the
value of Rs, according to the following table:

                      Range of Rs            Number of cycles

                         &0 -- &1            1S + 1I
                         &2 -- &7            1S + 2I
                         &8 -- &1F           1S + 3I
                        &20 -- &7F           1S + 4I
                        &80 -- &1FF          1S + 5I
                       &200 -- &7FF          1S + 6I
                       &800 -- &1FFF         1S + 7I
                      &2000 -- &7FFF         1S + 8I
                      &8000 -- &1FFFF        1S + 9I
                     &20000 -- &7FFFF        1S + 10I
                     &80000 -- &1FFFFF       1S + 11I
                    &200000 -- &7FFFFF       1S + 12I
                    &800000 -- &1FFFFFF      1S + 13I
                   &2000000 -- &7FFFFFF      1S + 14I