📄 addaboard.c
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#if 0
ulTemp = ulTemp | ((ulData << 24) & 0xFF000000);
ulTemp = ulTemp | ((ulData << 8) & 0x00FF0000);
ulTemp = ulTemp | ((ulData >> 8) & 0x0000FF00);
ulTemp = ulTemp | ((ulData >> 24) & 0x000000FF);
#else
ulTemp = ulData;
#endif /* if 0 */
return(ulTemp);
}
/******************************************************************************
TITLE: vmeWriteLong
DESC: routine to write Long data to a VME address
PARAM: iVmeAddr - VME address to write
ulData - data to be written
RETURN: none
******************************************************************************/
void vmeWriteLong(int iVmeAddr, unsigned long ulData)
{
unsigned int * pVmeAddr;
unsigned long ulTemp;
#if 0
ulTemp = 0;
ulTemp = ulTemp | ((ulData << 24)& 0xFF000000);
ulTemp = ulTemp | ((ulData << 8)& 0x00FF0000);
ulTemp = ulTemp | ((ulData >> 8)& 0x0000FF00);
ulTemp = ulTemp | ((ulData >> 24)& 0x000000FF);
#else
ulTemp = ulData;
#endif /* if 0 */
pVmeAddr = ((unsigned int *)iVmeAddr);
*pVmeAddr = ulTemp;
}
/******************************************************************************
TITLE: addaDDSRegWrite
DESC: routine to write DDS register in AD_DA board
PARAM: pAddaBrdDev - pointer to ADDABRD_DEV device structure
iRegNum - which register to write
pArray - pointer to data buffer
iList - switch for list debug information
RETURN: OK - operation runs successfully
ERROR - operation runs failed
NOTE: data buffer pArray should be 2 Quadlet, i.e. 64 bit;
high Quadlet should be holded in the high Quadlet of pArray, i.e. pArray[1]，
low Quadlet should be holded in the low Quadlet of pArray， i.e. pArray[0]
******************************************************************************/
STATUS addaDDSRegWrite(ADDABRD_DEV *pAddaBrdDev, int iRegNum, int *pArray, int iList)
{
int i;
unsigned long ulRegData;
unsigned long ulTempData;
int *pDataBaseBand;
int pTemp[2];
if (iRegNum & 0xffffffe0)
{
logMsg("addaDDSRegWrite: reg Number ERROR\n", 0, 0, 0, 0, 0, 0);
return(ERROR);
}
pTemp[0] = pArray[0];
pTemp[1] = pArray[1];
if (iList)
{
logMsg("addaDDSRegWrite: pArray[0] = 0x%8x\n", pTemp[0], 0, 0, 0, 0, 0);
logMsg("addaDDSRegWrite: pArray[1] = 0x%8x\n", pTemp[1], 0, 0, 0, 0, 0);
}
/* 1. write data to 64 bit CTL reg */
pDataBaseBand = (int*)(pAddaBrdDev->iVmeBaseAddr + DDS_CTL_REG_OFFSET_TO_DDC_REG + ADDA_DDS_CTL_REG1_OFFSET); /* CTL reg 1 */
*pDataBaseBand = pArray[1];
if (iList)
{
logMsg("addaDDSRegWrite: write High Quadlet to ctrl reg 1\n", 0, 0, 0, 0, 0, 0);
logMsg("addaDDSRegWrite: addr of CTL reg 1 = 0x%8x\n", (int)pDataBaseBand, 0, 0, 0, 0, 0);
ulTempData = *pDataBaseBand;
logMsg("addaDDSRegWrite: CTL reg 1 = 0x%8x\n", ulTempData, 0, 0, 0, 0, 0);
}
pDataBaseBand = (int*)(pAddaBrdDev->iVmeBaseAddr + DDS_CTL_REG_OFFSET_TO_DDC_REG + ADDA_DDS_CTL_REG2_OFFSET); /* CTL reg 2 */
*pDataBaseBand = pArray[0];
if (iList)
{
logMsg("addaDDSRegWrite: write low Quadlet to ctrl reg 2\n", 0, 0, 0, 0, 0, 0);
logMsg("addaDDSRegWrite: addr of CTL reg 2 = 0x%8x\n", (int)pDataBaseBand, 0, 0, 0, 0, 0);
ulTempData = *pDataBaseBand;
logMsg("addaDDSRegWrite: CTL reg 2 = 0x%8x\n", ulTempData, 0, 0, 0, 0, 0);
}
/* 2. write 16 bit instruction reg, set bit 15 to 1 for write */
pDataBaseBand = (int*)(pAddaBrdDev->iVmeBaseAddr + DDS_CTL_REG_OFFSET_TO_DDC_REG + ADDA_DDS_CFG_REG_OFFSET);
ulRegData = iRegNum & 0x0000001f;
*pDataBaseBand = (int)ulRegData;
if (iList)
{
logMsg("addaDDSRegWrite: addr of INST reg = 0x%8x\n", (int)pDataBaseBand, 0, 0, 0, 0, 0);
logMsg("addaDDSRegWrite: DATA to write = 0x%8x\n", (int)ulRegData, 0, 0, 0, 0, 0);
ulTempData = *pDataBaseBand;
logMsg("addaDDSRegWrite: INST reg = 0x%8x\n", ulTempData, 0, 0, 0, 0, 0);
}
return(OK);
}
/******************************************************************************
TITLE: addaDDSRegRead
DESC: routine to read DDS register in AD_DA board
PARAM: pAddaBrdDev - pointer to ADDABRD_DEV device structure
iRegNum - which register to read
pArray - pointer to data buffer
iList - switch for list debug information
RETURN: OK - operation runs successfully
ERROR - operation runs failed
NOTE: data buffer pArray should be 2 Quadlet, i.e. 64 bit;
high Quadlet should be holded in the high Quadlet of pArray, i.e. pArray[1]，
low Quadlet should be holded in the low Quadlet of pArray， i.e. pArray[0]
******************************************************************************/
STATUS addaDDSRegRead(ADDABRD_DEV *pAddaBrdDev, int iRegNum, int *pArray, int iList)
{
int i;
unsigned long ulRegData;
unsigned long ulTempData;
int *pDataBaseBand;
int pTemp[2];
if (iRegNum & 0xffffffe0)
{
logMsg("addaDDSRegRead: reg Number ERROR\n", 0, 0, 0, 0, 0, 0);
return(ERROR);
}
/* 1. write 16 bit instruction reg, set bit 14 to 1 for read */
pDataBaseBand = (int*)(pAddaBrdDev->iVmeBaseAddr + DDS_CTL_REG_OFFSET_TO_DDC_REG + ADDA_DDS_CFG_REG_OFFSET);
ulRegData = 0x00000080 | (iRegNum & 0x0000001f);
*pDataBaseBand = (int)ulRegData;
if (iList)
{
logMsg("addaDDSRegRead: addr of INST reg = 0x%8x\n", (int)pDataBaseBand, 0, 0, 0, 0, 0);
logMsg("addaDDSRegRead: DATA to write = 0x%8x\n", (int)ulRegData, 0, 0, 0, 0, 0);
ulTempData = *pDataBaseBand;
logMsg("addaDDSRegRead: INST reg = 0x%8x\n", ulTempData, 0, 0, 0, 0, 0);
}
/* 2. wait for a while */
taskDelay(1);
if (iList)
{
logMsg("addaDDSRegRead: wait for a while\n", 0, 0, 0, 0, 0, 0);
}
/* 3. read register data */
pDataBaseBand = (int*)(pAddaBrdDev->iVmeBaseAddr + DDS_CTL_REG_OFFSET_TO_DDC_REG + ADDA_DDS_STA_REG1_OFFSET); /* STA reg 1 */
ulTempData = *pDataBaseBand;
pArray[1] = ulTempData;
if (iList)
{
logMsg("addaDDSRegRead: read High Quadlet to buffer 1\n", 0, 0, 0, 0, 0, 0);
logMsg("addaDDSRegRead: addr of STA reg 1 = 0x%8x\n", (int)pDataBaseBand, 0, 0, 0, 0, 0);
logMsg("addaDDSRegRead: STA reg 1 = 0x%8x\n", ulTempData, 0, 0, 0, 0, 0);
}
pDataBaseBand = (int*)(pAddaBrdDev->iVmeBaseAddr + DDS_CTL_REG_OFFSET_TO_DDC_REG + ADDA_DDS_STA_REG2_OFFSET); /* STA reg 2 */
ulTempData = *pDataBaseBand;
pArray[0] = ulTempData;
if (iList)
{
logMsg("addaDDSRegRead: read low Quadlet to buffer 0\n", 0, 0, 0, 0, 0, 0);
logMsg("addaDDSRegRead: addr of STA reg 2 = 0x%8x\n", (int)pDataBaseBand, 0, 0, 0, 0, 0);
logMsg("addaDDSRegRead: STA reg 2 = 0x%8x\n", ulTempData, 0, 0, 0, 0, 0);
}
return(OK);
}
/******************************************************************************
TITLE: addaDDSGlobalReset
DESC: routine to reset DDS in AD_DA board
PARAM: pAddaBrdDev - pointer to ADDABRD_DEV device structure
RETURN: OK - operation runs successfully
ERROR - operation runs failed
******************************************************************************/
STATUS addaDDSGlobalReset(ADDABRD_DEV *pAddaBrdDev)
{
int *pDataBaseBand;
/* write data to Global Reset reg */
pDataBaseBand = (int*)(pAddaBrdDev->iVmeBaseAddr + DDS_CTL_REG_OFFSET_TO_DDC_REG + ADDA_DDS_GRST_CS_REG_OFFSET); /* Global Reset reg */
*pDataBaseBand = 0x47;
return(OK);
}
/******************************************************************************
TITLE: addaDDSIOReset
DESC: routine to reset DDS I/O in AD_DA board
PARAM: pAddaBrdDev - pointer to ADDABRD_DEV device structure
RETURN: OK - operation runs successfully
ERROR - operation runs failed
******************************************************************************/
STATUS addaDDSIOReset(ADDABRD_DEV *pAddaBrdDev)
{
int *pDataBaseBand;
/* write data to I/O Reset reg */
pDataBaseBand = (int*)(pAddaBrdDev->iVmeBaseAddr + DDS_CTL_REG_OFFSET_TO_DDC_REG + ADDA_DDS_IORST_CS_REG_OFFSET); /* I/O Reset reg */
*pDataBaseBand = 0x47;
return(OK);
}
/******************************************************************************TITLE: addaDACRegWrite
DESC: routine to write DAC register in AD_DA board
PARAM: pAddaBrdDev - pointer to ADDABRD_DEV device structure iRegNum - which register to write ulData - pointer to data buffer
iList - switch for list debug informationRETURN: OK - operation runs successfully ERROR - operation runs failedNOTE: data buffer ulData should be BYTE, i.e. 8 bit;
******************************************************************************/
STATUS addaDACRegWrite(ADDABRD_DEV *pAddaBrdDev, int iRegNum, unsigned long ulData, int iList)
{ int i; unsigned long ulRegData; unsigned long ulTempData; int *pDataBaseBand; int pTemp[2]; if (iRegNum & 0xffffffe0) { logMsg("addaDACRegWrite: reg Number ERROR\n", 0, 0, 0, 0, 0, 0);
return(ERROR); } /* 1. write 16 bit instruction reg, set bit 15 to 1 for write */
pDataBaseBand = (int*)(pAddaBrdDev->iVmeBaseAddr + DAC_MODE_CTL_REG_TO_DDC_REG + ADDA_DAC_CTL_REG_OFFSET); /* CTL reg */
ulRegData = ((iRegNum & 0x0000001f) << 8) | (ulData & 0xff);
*pDataBaseBand = (int)ulRegData; if (iList) { logMsg("addaDACRegWrite: addr of INST reg = 0x%8x\n", (int)pDataBaseBand, 0, 0, 0, 0, 0);
logMsg("addaDACRegWrite: DATA to write = 0x%8x\n", (int)ulRegData, 0, 0, 0, 0, 0);
ulTempData = *pDataBaseBand; logMsg("addaDACRegWrite: INST reg = 0x%8x\n", ulTempData, 0, 0, 0, 0, 0);
} return(OK);}/******************************************************************************TITLE: addaDACRegRead
DESC: routine to read DAC register in AD_DA board
PARAM: pAddaBrdDev - pointer to ADDABRD_DEV device structure iRegNum - which register to read pRegData - pointer to data buffer
iList - switch for list debug informationRETURN: OK - operation runs successfully ERROR - operation runs failedNOTE: data buffer ulData should be BYTE, i.e. 8 bit;
******************************************************************************/STATUS addaDACRegRead(ADDABRD_DEV *pAddaBrdDev, int iRegNum, unsigned long *pRegData, int iList)
{ int i; unsigned long ulRegData; unsigned long ulTempData; int *pDataBaseBand; int pTemp[2]; if (iRegNum & 0xffffffe0) { logMsg("addaDACRegRead: reg Number ERROR\n", 0, 0, 0, 0, 0, 0);
return(ERROR); } /* 1. write 16 bit instruction reg */
pDataBaseBand = (int*)(pAddaBrdDev->iVmeBaseAddr + DAC_MODE_CTL_REG_TO_DDC_REG + ADDA_DAC_CTL_REG_OFFSET);
ulRegData = (0x00000080 | (iRegNum & 0x0000001f)) << 8;
*pDataBaseBand = (int)ulRegData; if (iList) { logMsg("addaDACRegRead: addr of INST reg = 0x%8x\n", (int)pDataBaseBand, 0, 0, 0, 0, 0);
logMsg("addaDACRegRead: DATA to write = 0x%8x\n", (int)ulRegData, 0, 0, 0, 0, 0);
ulTempData = *pDataBaseBand; logMsg("addaDACRegRead: INST reg = 0x%8x\n", ulTempData, 0, 0, 0, 0, 0);
} /* 2. wait for a while */ taskDelay(1); if (iList) { logMsg("addaDACRegRead: wait for a while\n", 0, 0, 0, 0, 0, 0);
} /* 3. read register data */ pDataBaseBand = (int*)(pAddaBrdDev->iVmeBaseAddr + DAC_MODE_CTL_REG_TO_DDC_REG + ADDA_DAC_STATUS_REG_OFFSET);
ulTempData = (*pDataBaseBand) & 0xff;
*pRegData = ulTempData;
if (iList) { logMsg("addaDACRegRead: addr of STA reg 1 = 0x%8x\n", (int)pDataBaseBand, 0, 0, 0, 0, 0);
logMsg("addaDACRegRead: reg(0x%.2x) = 0x%.2x\n", iRegNum, ulTempData, 0, 0, 0, 0);
logMsg("addaDACRegRead: pRegData(0x%.8x) = 0x%.2x\n", (int)pRegData, *pRegData, 0, 0, 0, 0);
} return(OK);
}/******************************************************************************
TITLE: AddaBrdDrvParmReset
DESC: routine to clear all driver specific parameter of ADDA board
PARAM: none
RETURN: none
******************************************************************************/
void AddaBrdDrvParmReset(void)
{
DriverNumber = 0;
NumberOfDevices = 0;
}
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