hfctlpmc.c

vxworks下跳频控制的驱动

         ucResult = (unsigned char)((uiResult & BYTE3_IN_WORD) >> 24);
         *(unsigned char *)iParam = ucResult;
         return(OK);

      case HFCTL_SET_LOCAL_MISC2:
         uiResult = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_BIGEND_PCI));
         uiResult = (uiResult & (~BYTE3_IN_WORD)) | ((iParam & BYTE0_IN_WORD) << 24);
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_BIGEND_PCI), uiResult);
         return(OK);

      case HFCTL_GET_EROMRANGE:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_EROMRR_PCI));
         return(OK);

      case HFCTL_SET_EROMRANGE:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_EROMRR_PCI), iParam);
         return(OK);

      case HFCTL_GET_EROM_BASE_ADRS:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_EROMBA_PCI));
         return(OK);

      case HFCTL_SET_EROM_BASE_ADRS:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_EROMBA_PCI), iParam);
         return(OK);

      case HFCTL_GET_LOCAL_BUS_0_REGION_DESC:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_LBRD0_PCI));
         return(OK);

      case HFCTL_SET_LOCAL_BUS_0_REGION_DESC:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_LBRD0_PCI), iParam);
         return(OK);

      case HFCTL_GET_LOCAL_RANGE_DIR_MASTER:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_DMRR_PCI));
         return(OK);

      case HFCTL_SET_LOCAL_RANGE_DIR_MASTER:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_DMRR_PCI), iParam);
         return(OK);

      case HFCTL_GET_LOCAL_BASE_ADRS_DIR_MASTER:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_DMLBAM_PCI));
         return(OK);

      case HFCTL_SET_LOCAL_BASE_ADRS_DIR_MASTER:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_DMLBAM_PCI), iParam);
         return(OK);

      case HFCTL_GET_LOCAL_BASE_ADRS_DIR_MASTER_IO:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_DMLBAI_PCI));
         return(OK);

      case HFCTL_SET_LOCAL_BASE_ADRS_DIR_MASTER_IO:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_DMLBAI_PCI), iParam);
         return(OK);

      case HFCTL_GET_PCI_BASE_ADRS_DIR_MASTER:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_DMPBAM_PCI));
         return(OK);

      case HFCTL_SET_PCI_BASE_ADRS_DIR_MASTER:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_DMPBAM_PCI), iParam);
         return(OK);

      case HFCTL_GET_PCI_CFG_ADRS_DIR_MASTER_IO:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_DMCFGA_PCI));
         return(OK);

      case HFCTL_SET_PCI_CFG_ADRS_DIR_MASTER_IO:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_DMCFGA_PCI), iParam);
         return(OK);

      case HFCTL_GET_LAS1RANGE:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_LAS1RR_PCI));
         return(OK);

      case HFCTL_SET_LAS1RANGE:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_LAS1RR_PCI), iParam);
         return(OK);

      case HFCTL_GET_LAS1BASEADDR:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_LAS1BA_PCI));
         return(OK);

      case HFCTL_SET_LAS1BASEADDR:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_LAS1BA_PCI), iParam);
         return(OK);

      case HFCTL_GET_LOCAL_BUS_1_REGION_DESC:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_LBRD1_PCI));
         return(OK);

      case HFCTL_SET_LOCAL_BUS_1_REGION_DESC:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_LBRD1_PCI), iParam);
         return(OK);

      case HFCTL_GET_DIR_MASTER_DUAL_ADRS_UPPER_ADRS:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_DMDAC_PCI));
         return(OK);

      case HFCTL_SET_DIR_MASTER_DUAL_ADRS_UPPER_ADRS:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_DMDAC_PCI), iParam);
         return(OK);

      case HFCTL_GET_PCI_ARBITER_CTL:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_PCIARB_PCI));
         return(OK);

      case HFCTL_SET_PCI_ARBITER_CTL:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_PCIARB_PCI), iParam);
         return(OK);

      case HFCTL_GET_PCI_ABORT_ADRS:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_PABTADR_PCI));
         return(OK);

      case HFCTL_SET_PCI_ABORT_ADRS:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_PABTADR_PCI), iParam);
         return(OK);

      case HFCTL_GET_P2LDOORBELL:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_RT_REG_P2LDBELL_PCI));
         return(OK);

      case HFCTL_SET_P2LDOORBELL:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_RT_REG_P2LDBELL_PCI), iParam);
         return(OK);

      case HFCTL_GET_L2PDOORBELL:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_RT_REG_L2PDBELL_PCI));
         return(OK);

      case HFCTL_SET_L2PDOORBELL:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_RT_REG_L2PDBELL_PCI), iParam);
         return(OK);

      case HFCTL_GET_DMA_CHAN_0_MODE:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_DMA_REG_DMAMODE0_PCI));
         return(OK);

      case HFCTL_SET_DMA_CHAN_0_MODE:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_DMA_REG_DMAMODE0_PCI), iParam);
         return(OK);

      case HFCTL_GET_DMA_CHAN_0_PCI_ADRS:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_DMA_REG_DMAPADR0_PCI));
         return(OK);

      case HFCTL_SET_DMA_CHAN_0_PCI_ADRS:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_DMA_REG_DMAPADR0_PCI), iParam);
         return(OK);

      case HFCTL_GET_DMA_CHAN_0_LOCAL_ADRS:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_DMA_REG_DMALADR0_PCI));
         return(OK);

      case HFCTL_SET_DMA_CHAN_0_LOCAL_ADRS:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_DMA_REG_DMALADR0_PCI), iParam);
         return(OK);

      case HFCTL_GET_DMA_CHAN_0_TRANS_SIZE:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_DMA_REG_DMASIZ0_PCI));
         return(OK);

      case HFCTL_SET_DMA_CHAN_0_TRANS_SIZE:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_DMA_REG_DMASIZ0_PCI), iParam);
         return(OK);

      case HFCTL_GET_DMA_CHAN_0_DESC_PTR:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_DMA_REG_DMADPR0_PCI));
         return(OK);

      case HFCTL_SET_DMA_CHAN_0_DESC_PTR:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_DMA_REG_DMADPR0_PCI), iParam);
         return(OK);

      case HFCTL_GET_DMA_CHAN_1_MODE:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_DMA_REG_DMAMODE1_PCI));
         return(OK);

      case HFCTL_SET_DMA_CHAN_1_MODE:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_DMA_REG_DMAMODE1_PCI), iParam);
         return(OK);

      case HFCTL_GET_DMA_CHAN_1_PCI_ADRS:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_DMA_REG_DMAPADR1_PCI));
         return(OK);

      case HFCTL_SET_DMA_CHAN_1_PCI_ADRS:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_DMA_REG_DMAPADR1_PCI), iParam);
         return(OK);

      case HFCTL_GET_DMA_CHAN_1_LOCAL_ADRS:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_DMA_REG_DMALADR1_PCI));
         return(OK);

      case HFCTL_SET_DMA_CHAN_1_LOCAL_ADRS:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_DMA_REG_DMALADR1_PCI), iParam);
         return(OK);

      case HFCTL_GET_DMA_CHAN_1_TRANS_SIZE:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_DMA_REG_DMASIZ1_PCI));
         return(OK);

      case HFCTL_SET_DMA_CHAN_1_TRANS_SIZE:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_DMA_REG_DMASIZ1_PCI), iParam);
         return(OK);

      case HFCTL_GET_DMA_CHAN_1_DESC_PTR:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_DMA_REG_DMADPR1_PCI));
         return(OK);

      case HFCTL_SET_DMA_CHAN_1_DESC_PTR:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_DMA_REG_DMADPR1_PCI), iParam);
         return(OK);

      case HFCTL_GET_DMA_CHAN_0_CMD_STATUS:
         *(unsigned char *)iParam = pciReadByte((int)(pHfctlDev->pciControllerSpace0 + PLX9656_DMA_REG_DMACSR0_PCI));
         return(OK);

      case HFCTL_SET_DMA_CHAN_0_CMD_STATUS:
         pciWriteByte((int)(pHfctlDev->pciControllerSpace0 + PLX9656_DMA_REG_DMACSR0_PCI), (unsigned char)iParam);
         return(OK);

      case HFCTL_GET_DMA_CHAN_1_CMD_STATUS:
         *(unsigned char *)iParam = pciReadByte((int)(pHfctlDev->pciControllerSpace0 + PLX9656_DMA_REG_DMACSR1_PCI));
         return(OK);

      case HFCTL_SET_DMA_CHAN_1_CMD_STATUS:
         pciWriteByte((int)(pHfctlDev->pciControllerSpace0 + PLX9656_DMA_REG_DMACSR1_PCI), (unsigned char)iParam);
         return(OK);

      case HFCTL_GET_DMA_ARBITRATION:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_DMA_REG_DMAARB_PCI));
         return(OK);

      case HFCTL_SET_DMA_ARBITRATION:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_DMA_REG_DMAARB_PCI), iParam);
         return(OK);

      case HFCTL_GET_DMA_THRESHOLD:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_DMA_REG_DMATHR_PCI));
         return(OK);

      case HFCTL_SET_DMA_THRESHOLD:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_DMA_REG_DMATHR_PCI), iParam);
         return(OK);

      case HFCTL_GET_DMA_DAC0:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_DMA_REG_DMADAC0_PCI));
         return(OK);

      case HFCTL_SET_DMA_DAC0:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_DMA_REG_DMADAC0_PCI), iParam);
         return(OK);

      case HFCTL_GET_DMA_DAC1:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_DMA_REG_DMADAC1_PCI));
         return(OK);

      case HFCTL_SET_DMA_DAC1:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_DMA_REG_DMADAC1_PCI), iParam);
         return(OK);

      case HFCTL_WAIT_LOCAL_DATA:
#if 0
         logMsg("HFCtlIoctl.HFCTL_WAIT_LOCAL_DATA: Enter.\n", 0, 0, 0, 0, 0, 0); 
         logMsg("HFCtlIoctl.HFCTL_WAIT_LOCAL_DATA: iParam = %d.\n", iParam, 0, 0, 0, 0, 0); 
#endif /* if 0 */
         iResult = semTake(pHfctlDev->semLocalData, iParam);
#if 0
         if (iResult == ERROR)
            {
            logMsg("HFCtlIoctl.HFCTL_WAIT_LOCAL_DATA: semTake() ERROR.\n", 0, 0, 0, 0, 0, 0); 
            }
#endif /* if 0 */
         
         return(iResult);

      case HFCTL_SET_MEM_TO_LSPACE0:
         pHfctlDev->iWhichSapce = HFCTL_DATASPACE_0;
         return(OK);

      case HFCTL_SET_MEM_TO_LSPACE1:
         pHfctlDev->iWhichSapce = HFCTL_DATASPACE_1;
         return(OK);

      case HFCTL_GET_MEM_SPACE:
         *(UINT32*)iParam = pHfctlDev->iWhichSapce;
         return(OK);
         
      case HFCTL_READ_BLOCK_RAM:
         pHfctlRamBlk = (HFCTL_RAM_BLOCK *)(iParam);
         pSrcBuffer = (unsigned long *)(pHfctlDev->boardDataSpace0 + pHfctlRamBlk->offset);
         pDestBuffer = (unsigned long *)(pHfctlRamBlk->buffer);

         for(i = 0; i < pHfctlRamBlk->count; i++)
            {
            *pDestBuffer++ = *pSrcBuffer++;
            }

         return(OK);
         
      case HFCTL_WRITE_BLOCK_RAM:
         pHfctlRamBlk = (HFCTL_RAM_BLOCK *)(iParam);
         pDestBuffer = (unsigned long *)(pHfctlDev->boardDataSpace0 + pHfctlRamBlk->offset);
         pSrcBuffer = (unsigned long *)(pHfctlRamBlk->buffer);

#if 0
         logMsg("HFCtlIoctl.HFCTL_WRITE_BLOCK_RAM: pSrcBuffer = 0x%.8x\n", *pSrcBuffer, 0, 0, 0, 0, 0);
#endif /* if 0 */

         for(i = 0; i < pHfctlRamBlk->count; i++)
            {
            *pDestBuffer++ = *pSrcBuffer++;
            }

#if 0
         pDestBuffer = (unsigned long *)(pHfctlDev->boardDataSpace0 + pHfctlRamBlk->offset);
         for(i = 0; i < pHfctlRamBlk->count; i++)
            {
            logMsg("HFCtlIoctl.HFCTL_WRITE_BLOCK_RAM: pDestBuffer = 0x%.8x\n", *pDestBuffer, 0, 0, 0, 0, 0);
            }
#endif /* if 0 */

         return(OK);
         
      case HFCTL_READ_FIFO:   /* read TX FIFO */
         pHfctlRamBlk = (HFCTL_RAM_BLOCK *)(iParam);
         pSrcBuffer = (unsigned long *)(pHfctlDev->boardDataSpace0 + HFCTL_FIFO_OFFSET);
         pDestBuffer = (unsigned long *)(pHfctlRamBlk->buffer);

         for(i = 0; i < pHfctlRamBlk->count; i++)
            {
            *pDestBuffer++ = *pSrcBuffer;
            }

         return(OK);
         
      case HFCTL_WRITE_FIFO:  /* write TX FIFO */
#if 0
         logMsg("HFCtlIoctl.HFCTL_WRITE_FIFO: enter.\n", 0, 0, 0, 0, 0, 0); 
#endif /* if 0 */
         pHfctlRamBlk = (HFCTL_RAM_BLOCK *)(iParam);
         pDestBuffer = (unsigned long *)(pHfctlDev->boardDataSpace0 + HFCTL_FIFO_OFFSET);
         pSrcBuffer = (unsigned long *)(pHfctlRamBlk->buffer);