hfctlpmc.c

vxworks下跳频控制的驱动

   pHfctlDev->devBusy = 1;
   return((int)pHfctlDev);
}

/******************************************************************************
TITLE:   HFCtlClose
DESC:    routine to close a hop freq control PMC card device
PARAM:   pHfctlDev   - pointer to HFCTL_DEV device structure
RETURN:  OK          - close the device successfully
         ERROR       - close the device failed with error
******************************************************************************/
int HFCtlClose(HFCTL_DEV *pHfctlDev)
{
   if (pHfctlDev->devCreated == 0)
      {
      errnoSet(HFCTL_DRIVER_NOT_CREATED);
      return(ERROR);
      }

   if (!(pHfctlDev->devBusy))
      {
      errnoSet(HFCTL_DRIVER_NOT_IN_USE);
      return(ERROR);
      }

   pHfctlDev->devBusy = 0;

   /* reset the PCI card for next use */

   /* end of card reset */

   return(OK);
}

/******************************************************************************
TITLE:   HFCtlRead
DESC:    routine to read data from hop freq control PMC card
PARAM:   pHfctlDev   - pointer to HFCTL_DEV device structure
         pRevBuf     - pointer to receive buffer
         iNum        - bytes number to read, should be multiple of 4
RETURN:  iNum        - bytes number have been read
******************************************************************************/
int HFCtlRead(HFCTL_DEV *pHfctlDev, char *pRevBuf, int iNum)
{
   int i;
   int iTmpNum;
   register unsigned int *lbuffer = (unsigned int *)pRevBuf;
   register unsigned int *source = (unsigned int *)(pHfctlDev->boardDataSpace0);

   if (pHfctlDev->iWhichSapce == HFCTL_DATASPACE_0)
      {
      source = (unsigned int *)(pHfctlDev->boardDataSpace0);
      }
   else
      {
      source = (unsigned int *)(pHfctlDev->boardDataSpace1);
      }

   iTmpNum = iNum / 4;
   for(i = 0; i < iTmpNum; i++)
      {
         *lbuffer = *source;
         lbuffer++;
         source++;
      }
   return(iNum);
}

/******************************************************************************
TITLE:   HFCtlWrite
DESC:    routine to write data to hop freq control PMC card
PARAM:   pHfctlDev   - pointer to HFCTL_DEV device structure
         pSrcBuf     - pointer to source buffer
         iNum        - bytes number to write, should be multiple of 4
RETURN:  iNum        - bytes number have been written
******************************************************************************/
int HFCtlWrite(HFCTL_DEV *pHfctlDev, char *pSrcBuf, int iNum)
{
   int i;
   int iTmpNum;
   register unsigned int *lbuffer = (unsigned int *)pSrcBuf;
   register unsigned int *destination = (unsigned int *)(pHfctlDev->boardDataSpace0);

   if (pHfctlDev->iWhichSapce == HFCTL_DATASPACE_0)
      {
      destination = (unsigned int *)(pHfctlDev->boardDataSpace0);
      }
   else
      {
      destination = (unsigned int *)(pHfctlDev->boardDataSpace1);
      }

   iTmpNum = iNum / 4;
   for(i = 0; i < iTmpNum; i++)
      {
         *destination = *lbuffer;
         lbuffer++;
         destination++;
      }
   return(iNum);
}

/******************************************************************************
TITLE:   HFCtlIoctl
DESC:    Routine to configure and control hop freq control PMC card
PARAM:   pHfctlDev   - pointer to HFCTL_DEV device structure
         iFunCode    - code for the desired action
         iParam      - data supplied to or from routine
RETURN:  OK          - operation was successful
         ERROR       - operation failed
******************************************************************************/
int HFCtlIoctl (HFCTL_DEV *pHfctlDev, int iFunCode, int iParam)
{
   int      i;
   unsigned long ulTemp = 1;
   int      iTemp = 1;
   int      iTemp1 = 0;
   int      iResult;
   int      iLength;
   UINT32   uiResult;
   unsigned char ucResult;
   unsigned char ucTemp;
   HFCTL_RAM_BLOCK *pHfctlRamBlk;
   unsigned long *pSrcBuffer;
   unsigned long *pDestBuffer;
   unsigned long *pFlagAdrs;

   switch (iFunCode)
      {
      case HFCTL_GET_INT_STATUS:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_RT_REG_INTCSR_PCI));
         return(OK);

      case HFCTL_SET_INT_STATUS:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_RT_REG_INTCSR_PCI), iParam);
         return(OK);
/*   
      case HFCTL_GET_PCI_BASE_ADRS_2:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_PCI_CFG_REG_BAR2_PCI));
         return(OK);

      case HFCTL_SET_PCI_BASE_ADRS_2:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_PCI_CFG_REG_BAR2_PCI), iParam);
         return(OK);

      case HFCTL_GET_PCI_COMMAND:
         uiResult = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_PCI_CFG_REG_PCI_CMD_PCI));
         uiResult = uiResult & 0xffff;
         *(UINT32*)iParam = uiResult;
         return(OK);

      case HFCTL_SET_PCI_COMMAND:
         uiResult = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_PCI_CFG_REG_PCI_CMD_PCI));
         uiResult = (uiResult & UPPER16) | (iParam & LOWER16);
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_PCI_CFG_REG_PCI_CMD_PCI), uiResult);
         return(OK);
*/     /* comment by chenxuhao at 2004-11-28 */

      case HFCTL_GET_RT_CNTRL:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_RT_REG_CNTRL_PCI));
         return(OK);

      case HFCTL_SET_RT_CNTRL:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_RT_REG_CNTRL_PCI), iParam);
         return(OK);

      case HFCTL_GET_RT_DEVID:
#if 0
         logMsg("HFCtlIoctl: HFCTL_GET_RT_DEVID = 0x%.8x\n", 
                (pHfctlDev->pciControllerSpace0 + PLX9656_RT_REG_PCIHIDR_PCI), 0, 0, 0, 0, 0);
#endif /* if 0 */
         uiResult = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_RT_REG_PCIHIDR_PCI));
#if 0
         logMsg("HFCtlIoctl: HFCTL_GET_RT_DEVID uiResult = 0x%.8x\n", uiResult, 0, 0, 0, 0, 0);
#endif /* if 0 */
         uiResult = (uiResult & UPPER16) >> 16;
#if 0
         logMsg("HFCtlIoctl: HFCTL_GET_RT_DEVID iParam = 0x%.8x\n", iParam, 0, 0, 0, 0, 0);
#endif /* if 0 */
         *(UINT32*)iParam = uiResult;
         return(OK);

      case HFCTL_GET_RT_VENID:
         uiResult = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_RT_REG_PCIHIDR_PCI));
         uiResult = uiResult & LOWER16;
         *(UINT32*)iParam = uiResult;
         return(OK);

      case HFCTL_GET_RT_REVID:
         uiResult = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_RT_REG_PCIHREV_PCI));
         uiResult = uiResult & BYTE0_IN_WORD;
         *(UINT32*)iParam = uiResult;
         return(OK);

      case HFCTL_GET_MAILBOX0:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_RT_REG_MBOX0_PCI));
         return(OK);

      case HFCTL_SET_MAILBOX0:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_RT_REG_MBOX0_PCI), iParam);
         return(OK);

      case HFCTL_GET_MAILBOX1:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_RT_REG_MBOX1_PCI));
         return(OK);

      case HFCTL_SET_MAILBOX1:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_RT_REG_MBOX1_PCI), iParam);
         return(OK);

      case HFCTL_GET_MAILBOX2:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_RT_REG_MBOX2_PCI));
         return(OK);

      case HFCTL_SET_MAILBOX2:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_RT_REG_MBOX2_PCI), iParam);
         return(OK);

      case HFCTL_GET_MAILBOX3:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_RT_REG_MBOX3_PCI));
         return(OK);

      case HFCTL_SET_MAILBOX3:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_RT_REG_MBOX3_PCI), iParam);
         return(OK);

      case HFCTL_GET_MAILBOX4:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_RT_REG_MBOX4_PCI));
         return(OK);

      case HFCTL_SET_MAILBOX4:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_RT_REG_MBOX4_PCI), iParam);
         return(OK);

      case HFCTL_GET_MAILBOX5:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_RT_REG_MBOX5_PCI));
         return(OK);

      case HFCTL_SET_MAILBOX5:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_RT_REG_MBOX5_PCI), iParam);
         return(OK);

      case HFCTL_GET_MAILBOX6:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_RT_REG_MBOX6_PCI));
         return(OK);

      case HFCTL_SET_MAILBOX6:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_RT_REG_MBOX6_PCI), iParam);
         return(OK);

      case HFCTL_GET_MAILBOX7:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_RT_REG_MBOX7_PCI));
         return(OK);

      case HFCTL_SET_MAILBOX7:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_RT_REG_MBOX7_PCI), iParam);
         return(OK);

      case HFCTL_GET_LAS0RANGE:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_LAS0RR_PCI));
         return(OK);

      case HFCTL_SET_LAS0RANGE:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_LAS0RR_PCI), iParam);
         return(OK);

      case HFCTL_GET_LAS0BASEADDR:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_LAS0BA_PCI));
         return(OK);

      case HFCTL_SET_LAS0BASEADDR:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_LAS0BA_PCI), iParam);
         return(OK);

      case HFCTL_GET_MODE_ARBR:
         *(UINT32*)iParam = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_MARBR_PCI));
         return(OK);

      case HFCTL_SET_MODE_ARBR:
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_MARBR_PCI), iParam);
         return(OK);

      case HFCTL_GET_BIG_ENDIAN:
         uiResult = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_BIGEND_PCI));
         uiResult = uiResult & BYTE0_IN_WORD;
         *(unsigned char *)iParam = uiResult;
         return(OK);

      case HFCTL_SET_BIG_ENDIAN:
         uiResult = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_BIGEND_PCI));
         uiResult = (uiResult & BYTE123_IN_WORD) | (iParam & BYTE0_IN_WORD);
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_BIGEND_PCI), uiResult);
         return(OK);

      case HFCTL_GET_LOCAL_MISC1:
#if 0
         ucResult = pciReadByte((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_LMISC1_PCI));
         logMsg("HFCtlIoctl: HFCTL_GET_LOCAL_MISC1. ucResult = 0x%.8x\n", ucResult, 0, 0, 0, 0, 0);
         *(unsigned char *)iParam = ucResult;
#endif /* if 0 */
         uiResult = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_BIGEND_PCI));
#if 0
         logMsg("HFCtlIoctl: HFCTL_GET_LOCAL_MISC1. uiResult = 0x%.8x\n", uiResult, 0, 0, 0, 0, 0);
#endif /* if 0 */
         ucResult = (unsigned char)((uiResult & BYTE1_IN_WORD) >> 8);
#if 0
         logMsg("HFCtlIoctl: HFCTL_GET_LOCAL_MISC1. ucResult = 0x%.2x\n", ucResult, 0, 0, 0, 0, 0);
#endif /* if 0 */
         *(unsigned char *)iParam = ucResult;
         return(OK);

      case HFCTL_SET_LOCAL_MISC1:
#if 0
         logMsg("HFCtlIoctl: HFCTL_SET_LOCAL_MISC1. iParam = 0x%.8x\n", iParam, 0, 0, 0, 0, 0);
         ucTemp = (unsigned char)(iParam & 0xff);
         logMsg("HFCtlIoctl: HFCTL_SET_LOCAL_MISC1. ucTemp = 0x%.8x\n", ucTemp, 0, 0, 0, 0, 0);
         logMsg("HFCtlIoctl: HFCTL_SET_LOCAL_MISC1. pciAddr = 0x%.8x\n", 
                (pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_LMISC1_PCI), 0, 0, 0, 0, 0);
         pciWriteByte((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_LMISC1_PCI), ucTemp);
#endif /* if 0 */
         uiResult = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_BIGEND_PCI));
#if 0
         logMsg("HFCtlIoctl: HFCTL_SET_LOCAL_MISC1. uiResult = 0x%.8x\n", uiResult, 0, 0, 0, 0, 0);
         logMsg("HFCtlIoctl: HFCTL_SET_LOCAL_MISC1. iParam = 0x%.8x\n", iParam, 0, 0, 0, 0, 0);
#endif /* if 0 */
         uiResult = (uiResult & (~BYTE1_IN_WORD)) | ((iParam & BYTE0_IN_WORD) << 8);
#if 0
         logMsg("HFCtlIoctl: HFCTL_SET_LOCAL_MISC1. (~BYTE1_IN_WORD) = 0x%.8x\n", (~BYTE1_IN_WORD), 0, 0, 0, 0, 0);
         logMsg("HFCtlIoctl: HFCTL_SET_LOCAL_MISC1. uiResult = 0x%.8x\n", uiResult, 0, 0, 0, 0, 0);
#endif /* if 0 */
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_BIGEND_PCI), uiResult);
         return(OK);

      case HFCTL_GET_PROT_AREA:
         uiResult = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_BIGEND_PCI));
         ucResult = (unsigned char)((uiResult & BYTE2_IN_WORD) >> 16);
         *(unsigned char *)iParam = ucResult;
         return(OK);

      case HFCTL_SET_PROT_AREA:
         uiResult = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_BIGEND_PCI));
         uiResult = (uiResult & (~BYTE2_IN_WORD)) | ((iParam & BYTE0_IN_WORD) << 16);
         pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_BIGEND_PCI), uiResult);
         return(OK);

      case HFCTL_GET_LOCAL_MISC2:
         uiResult = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_BIGEND_PCI));