hfctlpmc.c

vxworks下跳频控制的驱动

/*            file number            */
/*
modification history
-,            2004, October, 12th      Release
-,            2004, January, 31st      add HFCTL_QUERY_DEHF_DATA_RDY to HFCtlIoctl()
                                       add HFCTL_CLEAR_DEHF_DATA_RDY_FLAG to HFCtlIoctl()
-,            2005, March, 11th        add HFCtlDrvParmReset().
-,            2005, March, 29th        add HFCTL_CLEAR_PCI_INT_VECTOR to HFCtlIoctl()
                                       add HFCTL_CLEAR_PCI_INT to HFCtlIoctl()
-,            2005, April, 1st         add HFCtlIntRemove().
-,            2005, April, 3rd         add HFCTL_GET_WORK_STATUS to HFCtlIoctl()
                                       add HFCTL_CLEAR_WORK_STATUS to HFCtlIoctl()
                                       add HFCTL_SET_WORK_STATUS to HFCtlIoctl()
-,            2005, April, 3rd         add HFCTL_ENABLE_DEHFDATA_FIFO_OUTPUT to HFCtlIoctl()
                                       add HFCTL_DISABLE_DEHFDATA_FIFO_OUTPUT to HFCtlIoctl()
*/

/****************************************************************
Module:       HFCtlPmc.c
Author:       
Description:  drivers for hop freq control PMC board 
                  written for vxWorks

       
****************************************************************/
/* Included Files */
#include <vxWorks.h>
#include <logLib.h>
#include <iv.h>
#include <intLib.h> 
#include <ioLib.h>
#include <iosLib.h>
#include <semLib.h>
#include <stdlib.h>
#include <stdio.h>
#include <sysLib.h>
#include <taskLib.h>
#include "../../../include/drv/hF1394Pmc/hFCtlPmc.h"
#include "../../../include/drv/hF1394Pmc/Plx9656.h"
#include "rs60x.h"
#include "i82378zb.h"

/* define some macro */

/* Global Variables */
int         HFCtl_Debug = 1;
int         iPciIntCount = 0;
int         i9656LocalIntCount = 0;
int         i9656LintRxFifoRdyCount = 0;
int         i9656LintTxHFDataRdyCount = 0;
int         i9656DmaIntCount = 0;
static int  pmcIntValue = 0;   /* PMC Interrupt Vector id */

static int  DriverNumber = 0;    /* driver number specified by iosDrvInstall() */
static int  NumberOfDevices = 0; /* number of devices created */

unsigned long *pTempBuffForRxFifo = (unsigned long *)0x5000000;

/* use for test */
int         iPciIntExecCount = 0;

/* system interrupt table */

IMPORT INT_HANDLER_DESC * sysIntTbl [256];

/* Forward Declaration */
LOCAL int HFCtlOpen(HFCTL_DEV *pHfctlDev);
LOCAL int HFCtlClose(HFCTL_DEV *pHfctlDev);
LOCAL int HFCtlRead(HFCTL_DEV *pHfctlDev, char *pRevBuf, int iNum);
LOCAL int HFCtlWrite(HFCTL_DEV *pHfctlDev, char *pSrcBuf, int iNum);
LOCAL int HFCtlIoctl (HFCTL_DEV *pHfctlDev, int iFunCode, int iParam);
LOCAL void HFCtlIntHandle(HFCTL_DEV *pHfctlDev);
STATUS PciBaseAddrRead (HFCTL_DEV *pHfctlDev, int instance);
unsigned long pciReadLong (int iPciAddr);
void pciWriteLong(int iPciAddr, unsigned long ulData);

/******************************************************************************
TITLE:   HFCtlDrv
DESC:    setup routine of hop freq control PMC Card 
PARAM:   none
RETURN:  DriverNumber   - driver number for freq control PMC Card driver

NOTE:    the routine should run only one time.
******************************************************************************/
int HFCtlDrv (void)
{
   if (DriverNumber > 0) 
      {
      return (DriverNumber);
      }
   DriverNumber = iosDrvInstall((FUNCPTR) NULL, (FUNCPTR) NULL,
                                 HFCtlOpen, HFCtlClose,
                                 HFCtlRead, HFCtlWrite,
                                 HFCtlIoctl);
   return(DriverNumber);
}

/******************************************************************************
TITLE:   HFCtlDevCreate
DESC:    device initialization of hop freq control PMC Card 
PARAM:   name        - device name
         pHfctlDev   - pointer to HFCTL_DEV device structure
RETURN:  OK          - device initialize successfully
         ERROR       - device initialize failed with error
******************************************************************************/
int HFCtlDevCreate (char *name, HFCTL_DEV *pHfctlDev)
{
   unsigned long ulTempData;
   unsigned char ucTempChar;

   if (DriverNumber <= 0)     /* driver not installed */
      {
      errnoSet(S_ioLib_NO_DRIVER);
      return(ERROR);
      }

   if (NumberOfDevices >= HFCTL_MAX_DEV)     /* too many devices created */
      {
      errnoSet(HFCTL_ALLOCATE_DEVICE_FAILED);
      return(ERROR);
      }

   if ((iosDevAdd(&(pHfctlDev->devHdr), name, DriverNumber)) != OK)
      {
      /* Specified device already exists */
      errnoSet(HFCTL_DEVICE_ALREADY_CREATED);
      return(ERROR);
      }

   /* search the card and read the base addr registers */
   if (PciBaseAddrRead(pHfctlDev, NumberOfDevices) != OK)
      {
      errnoSet(HFCTL_HARDWARE_INIT_FAILED);
      return(ERROR);
      }

#if 0
   if (HFCtl_Debug)
      {
      logMsg("HFCtlDevCreate: PciBaseAddrRead() successfully.\n", 0, 0, 0, 0, 0, 0);
      }
#endif /* if 0 */
/***************************/
   /* creaete semphore for driver */
   pHfctlDev->semLocalData = semBCreate(SEM_Q_PRIORITY, SEM_EMPTY);
   if (pHfctlDev->semLocalData == NULL)
      {
      errnoSet(HFCTL_CREATE_SEMAPHORE_FAILED);
      return (ERROR);
      }

   pHfctlDev->semDmaDone = semBCreate(SEM_Q_PRIORITY, SEM_EMPTY);
   if (pHfctlDev->semDmaDone == NULL)
      {
      semDelete(pHfctlDev->semLocalData);
      errnoSet(HFCTL_CREATE_SEMAPHORE_FAILED);
      return (ERROR);
      }
   
   pHfctlDev->semMailBox = semBCreate(SEM_Q_PRIORITY, SEM_EMPTY);
   if (pHfctlDev->semMailBox == NULL)
      {
      semDelete(pHfctlDev->semLocalData);
      semDelete(pHfctlDev->semDmaDone);
      errnoSet(HFCTL_CREATE_SEMAPHORE_FAILED);
      return (ERROR);
      }

   pHfctlDev->semRxFifoRdy = semBCreate(SEM_Q_PRIORITY, SEM_EMPTY);
   if (pHfctlDev->semRxFifoRdy == NULL)
      {
      semDelete(pHfctlDev->semLocalData);
      semDelete(pHfctlDev->semDmaDone);
      semDelete(pHfctlDev->semMailBox);
      errnoSet(HFCTL_CREATE_SEMAPHORE_FAILED);
      return (ERROR);
      }
   /* end of semphore creation */
/***************************/

#if 0
   if (HFCtl_Debug)
      {
      logMsg("HFCtlDevCreate: all semphores create successfully.\n", 0, 0, 0, 0, 0, 0);
      }
#endif /* if 0 */
/***************************/
   /* configure the board */
   /* reset the card */
   ulTempData = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_RT_REG_CNTRL_PCI));
#if 0
   if (HFCtl_Debug)
      {
      logMsg("HFCtlDevCreate: before reset PLX9656 CNTRL = 0x%.8x.\n", ulTempData, 0, 0, 0, 0, 0);
      }
#endif /* if 0 */
   ulTempData = ulTempData | DATA_BIT30;
#if 0
   if (HFCtl_Debug)
      {
      logMsg("HFCtlDevCreate: set value for CNTRL = 0x%.8x.\n", ulTempData, 0, 0, 0, 0, 0);
      }
#endif /* if 0 */
   pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_RT_REG_CNTRL_PCI), ulTempData);
#if 0
   if (HFCtl_Debug)
      {
      ulTempData = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_RT_REG_CNTRL_PCI));
      logMsg("HFCtlDevCreate: resetting PLX9656 CNTRL = 0x%.8x.\n", ulTempData, 0, 0, 0, 0, 0);
      }
#endif /* if 0 */
   taskDelay(1);
   ulTempData = ulTempData & ~DATA_BIT30;    /* clear software reset bit */
   pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_RT_REG_CNTRL_PCI), ulTempData);
#if 0
   if (HFCtl_Debug)
      {
      ulTempData = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_RT_REG_CNTRL_PCI));
      logMsg("HFCtlDevCreate: after reset PLX9656 CNTRL = 0x%.8x.\n", ulTempData, 0, 0, 0, 0, 0);
      }
#endif /* if 0 */
   /* end of RESET */

   /* clear local interrupt */
   ulTempData = 1;
   pciWriteLong((int)(pHfctlDev->boardDataSpace0 + HFCTL_CARD_LINT_CLR_REG), ulTempData);

   /* config LAS0 to access */
   /* get LAS0BA */
   ulTempData = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_LAS0BA_PCI));;
   /* set LAS0BA bit 0 to 1 */
   ulTempData = ulTempData | DATA_BIT0;
   pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_LAS0BA_PCI), ulTempData);

   /* config MARBR */
   ulTempData = 0x00210010;
   pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_MARBR_PCI), ulTempData);
   
   /* config BIGEND */
   ucTempChar = 0xee;
   pciWriteByte((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_BIGEND_PCI), ucTempChar);

   /* config LMISC1 */
   ucTempChar = 0x05;
   pciWriteByte((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_LMISC1_PCI), ucTempChar);

   /* config LMISC2 */
   ucTempChar = 0x01; /* enable READY# timeOut */
   pciWriteByte((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_LMISC2_PCI), ucTempChar);

   /* config LBRD0 */
   ulTempData = 0x80430343;
   pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_LOCAL_CFG_REG_LBRD0_PCI), ulTempData);
   /* end of config LAS0 */

   /* config DMA0 function */
   /* config DMAMODE0 */
   ulTempData = 0x00030043;
   pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_DMA_REG_DMAMODE0_PCI), ulTempData);
   /* end of config DMA0 function */

   /* end of board configuration */
/***************************/

/***************************/
   /* interrupt clear and install */
   /* INTCSR */
   pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_RT_REG_INTCSR_PCI), 0x0F0000A0);
   /* QSR */
   ulTempData = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_MSG_QUE_REG_QSR_PCI));
   ulTempData = ulTempData | DATA_BIT4 | DATA_BIT6;
   pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_MSG_QUE_REG_QSR_PCI), ulTempData);
   /* DMAMODE0 */
   ulTempData = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_DMA_REG_DMAMODE0_PCI));
   ulTempData = ulTempData & ~DATA_BIT10;
   pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_DMA_REG_DMAMODE0_PCI), ulTempData);
   /* DMADPR0 */
   ulTempData = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_DMA_REG_DMADPR0_PCI));
   ulTempData = ulTempData & ~DATA_BIT2;
   pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_DMA_REG_DMADPR0_PCI), ulTempData);
   /* DMAMODE1 */
   ulTempData = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_DMA_REG_DMAMODE1_PCI));
   ulTempData = ulTempData & ~DATA_BIT10;
   pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_DMA_REG_DMAMODE1_PCI), ulTempData);
   /* DMADPR1 */
   ulTempData = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_DMA_REG_DMADPR1_PCI));
   ulTempData = ulTempData & ~DATA_BIT2;
   pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_DMA_REG_DMADPR1_PCI), ulTempData);
   /* CNTRL */
   ulTempData = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_RT_REG_CNTRL_PCI));
   ulTempData = ulTempData | DATA_BIT20 | DATA_BIT21;
   pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_RT_REG_CNTRL_PCI), ulTempData);
   /* OPQIS */
   ulTempData = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_MSG_QUE_REG_OPQIS_PCI));
   ulTempData = ulTempData & ~DATA_BIT3;
   pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_MSG_QUE_REG_OPQIS_PCI), ulTempData);
   /* OPQIM */
   ulTempData = pciReadLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_MSG_QUE_REG_OPQIM_PCI));
   ulTempData = ulTempData | DATA_BIT3;
   pciWriteLong((int)(pHfctlDev->pciControllerSpace0 + PLX9656_MSG_QUE_REG_OPQIM_PCI), ulTempData);

   if (intConnect(INUM_TO_IVEC(pmcIntValue), HFCtlIntHandle, (int)pHfctlDev) == ERROR)
   {
      semDelete(pHfctlDev->semLocalData);
      semDelete(pHfctlDev->semDmaDone);
      semDelete(pHfctlDev->semMailBox);
      errnoSet(HFCTL_INT_HANDLER_INSTALL_FAILED);
      return(ERROR);
  }
   /* Enable interrupts */
   intEnable (pmcIntValue);
   /* end of interrupt install */
/***************************/

   NumberOfDevices++;
#if 0
   if (HFCtl_Debug)
      {
      fprintf(stderr, "\n\rNumberOfDevices = 0x%d", NumberOfDevices);
      }
#endif /* if 0 */
   pHfctlDev->devCreated = 1;    /* device created */
   pHfctlDev->devBusy = 0;       /* device available to be used */
   pHfctlDev->iWhichSapce = HFCTL_DATASPACE_0;  /* default data space is 0 (PCIBAR2) */
   return (OK);
}

/******************************************************************************
TITLE:   HFCtlOpen
DESC:    routine to open a hop freq control PMC card device
PARAM:   pHfctlDev   - pointer to HFCTL_DEV device structure
         
RETURN:  pHfctlDev   - file descriptor for opened device
         ERROR       - device cannot be open with error
******************************************************************************/
int HFCtlOpen(HFCTL_DEV *pHfctlDev)
{
   if (pHfctlDev->devCreated == 0)
      {
      errnoSet(HFCTL_DRIVER_NOT_CREATED);
      return(ERROR);
      }

   if (pHfctlDev->devBusy)
      {
      errnoSet(HFCTL_DRIVER_IN_USE);
      return(ERROR);
      }