lcdconf.h

ucgu最新版本 4.14

#define LCD_REG12 (LCD_BITSPERPIXEL*(LCD_VXSIZE-LCD_XSIZE)/16) /* Memory Address offset (usually 0) */
#define LCD_REG13 LCD_REG5                                     /* Vert. screen 1 size, lsb */
#define LCD_REG14 LCD_REG6                                     /* Vert. screen 1 size, msb */

#define LCD_REG18 (0x1)                                        /* GPIO0: output  */
#define LCD_REG19 (0x1)                                        /* GPIO0: 1: enable display  */
#define LCD_REG1B (0)                                          /* No swivel mode  (use 0xc0 for alt.swivel)  */
#define LCD_REG1C (0x78)                                       /* bytes per line (stride, for swivel mode only)  */

/*********************************************************************
*
*                   Init sequence for 16 bit access
*/

#if !LCD_SWAP_BYTE_ORDER
  #define LCD_WRITE_REGLH(Adr, d0, d1) LCD_WRITE_REG(Adr, ((d0)<<8) | (d1))
#else
  #define LCD_WRITE_REGLH(Adr, d0, d1) LCD_WRITE_REG(Adr, ((d1)<<8) | (d0))
#endif

#define LCD_INIT_CONTROLLER()                                                                    \
        LCD_WRITE_REGLH(0x00>>1,LCD_REG0, LCD_REG1);                                             \
        LCD_WRITE_REGLH(0x02>>1,LCD_REG2, LCD_REG3);                                             \
        LCD_WRITE_REGLH(0x04>>1,LCD_REG4, LCD_REG5);                                             \
        LCD_WRITE_REGLH(0x06>>1,LCD_REG6, LCD_REG7);                                             \
        LCD_WRITE_REGLH(0x08>>1,LCD_REG8, LCD_REG9);                                             \
        LCD_WRITE_REGLH(0x0a>>1,LCD_REGA, LCD_REGB);                                             \
        LCD_WRITE_REGLH(0x0c>>1,LCD_REGC, LCD_REGD);                                             \
        LCD_WRITE_REG  (0x0e>>1,0x00);                 /* 0, screen 2 start l*/                  \
        LCD_WRITE_REG  (0x10>>1,0x00);                 /* screen 2 start h */                    \
        LCD_WRITE_REGLH(0x12>>1,LCD_REG12, LCD_REG13); /* mem adr. offset, screen 1 vsize(lsb)*/ \
        LCD_WRITE_REGLH(0x14>>1,LCD_REG14, 0);                                                   \
        LCD_WRITE_REGLH(0x18>>1,LCD_REG18, LCD_REG19);                                                   \
        LCD_WRITE_REGLH(0x1a>>1,0, LCD_REG1B);                                                   \
        LCD_WRITE_REGLH(0x1c>>1,LCD_REG1C, 0)

/*********************************************************************
*
*            ARM default configuration (Phytec AT91)
*
**********************************************************************
*/
#elif defined (TARGET_AT91_PHYTEC)
  #define LCD_XSIZE      (320)   /* X-resolution of LCD, Logical coor. */
  #define LCD_YSIZE      (240)   /* Y-resolution of LCD, Logical coor. */
  #define LCD_BITSPERPIXEL (8)
  #define LCD_CONTROLLER 1375
  #define LCD_SWAP_BYTE_ORDER (1)

  #define LCD_READ_MEM(Off)            *((U16*)         (0x6040000+(((U32)(Off))<<1)))
  #define LCD_WRITE_MEM(Off,data)      *((U16*)         (0x6040000+(((U32)(Off))<<1)))=data
  #define LCD_READ_REG(Off)            *((volatile U16*)(0x605ffe0+(((U16)(Off))<<1)))
  #define LCD_WRITE_REG(Off,data)      *((volatile U16*)(0x605ffe0+(((U16)(Off))<<1)))=data

/*********************************************************************
*
*                   Define contents of registers
*/

#define LCD_REG0  (0)                                          /* Product code */

#define LCD_REG1  (0x23)                                       /* Mode reg 0.    0 for 4 bit mono LCD */            \
                                                               /*                1 for 8 bit mono LCD */            \
                                                               /*             0x23 for 8 bit color LCD */           \
                 |(1<<2)                                       /*             Mask FPSHIFT during h.non-display */

#define LCD_REG2 ((3<<6)                                       /* Mode reg 1: Bits per pixel 0:1, 1:2, 2:4, 3:8 */  \
                 |(1<<5)                                       /* High performance bit for accel. of CPU access */  \
                 |(1<<4)                                       /* Input clock divide */                             \
                 |(0<<3)                                       /* Display blank */                                  \
                 |(0<<2)                                       /* Frame repeat */                                   \
                 |(0<<1)                                       /* HW video invert enable */                         \
                 |(0<<0))                                      /* SW video invert */

#define LCD_REG3                                               /* Mode reg 2. 0 for 4 bit mono LCD */               \
                  (0<<7)                                       /* LUT bypass */                                     \
                 |(0<<3)                                       /* LCDPWR override */                                \
                 |(0<<2)                                       /* hw power save enable */                           \
                 |(3<<0)                                       /* Software power save :3 = normal operation */

#define LCD_REG4 (LCD_XSIZE/8-1)                               /* horizontal panel size*/
#define LCD_REG5 ((LCD_YSIZE-1)&255)                           /* Vert. panel size, lsb */
#define LCD_REG6 ((LCD_YSIZE-1)>>8)                            /* Vert. panel size, msb */
#define LCD_REG7 (0)                                           /* FPLine start position (TFT only) */
#define LCD_REG8 (31)                                          /* H.non display period   (0 usually O.K.)*/
#define LCD_REG9 (0)                                           /* FPFrame start pos.    (TFT only) */
#define LCD_REGA (0)                                           /* v.non display period  */
#define LCD_REGB (0)                                           /* mod rate register     0: every frame */
#define LCD_REGC (0)                                           /* Screen 1 start lsb    */
#define LCD_REGD (0)                                           /* Screen 1 start msb    */

#define LCD_REG12 (LCD_BITSPERPIXEL*(LCD_VXSIZE-LCD_XSIZE)/16) /* Memory Address offset (usually 0) */
#define LCD_REG13 LCD_REG5                                     /* Vert. screen 1 size, lsb */
#define LCD_REG14 LCD_REG6                                     /* Vert. screen 1 size, msb */

#define LCD_REG18 (0x1)                                        /* GPIO0: output  */
#define LCD_REG19 (0x1)                                        /* GPIO0: 1: enable display  */
#define LCD_REG1B (0)                                          /* No swivel mode  (use 0xc0 for alt.swivel)  */
#define LCD_REG1C (0x78)                                       /* bytes per line (stride, for swivel mode only)  */

/*********************************************************************
*
*                   Init sequence for 16 bit access
*/

#if !LCD_SWAP_BYTE_ORDER
  #define LCD_WRITE_REGLH(Adr, d0, d1) LCD_WRITE_REG(Adr, ((d0)<<8) | (d1))
#else
  #define LCD_WRITE_REGLH(Adr, d0, d1) LCD_WRITE_REG(Adr, ((d1)<<8) | (d0))
#endif

#define LCD_INIT_CONTROLLER()                                                                    \
        LCD_WRITE_REGLH(0x00>>1,LCD_REG0, LCD_REG1);                                             \
        LCD_WRITE_REGLH(0x02>>1,LCD_REG2, LCD_REG3);                                             \
        LCD_WRITE_REGLH(0x04>>1,LCD_REG4, LCD_REG5);                                             \
        LCD_WRITE_REGLH(0x06>>1,LCD_REG6, LCD_REG7);                                             \
        LCD_WRITE_REGLH(0x08>>1,LCD_REG8, LCD_REG9);                                             \
        LCD_WRITE_REGLH(0x0a>>1,LCD_REGA, LCD_REGB);                                             \
        LCD_WRITE_REGLH(0x0c>>1,LCD_REGC, LCD_REGD);                                             \
        LCD_WRITE_REG  (0x0e>>1,0x00);                 /* 0, screen 2 start l*/                  \
        LCD_WRITE_REG  (0x10>>1,0x00);                 /* screen 2 start h */                    \
        LCD_WRITE_REGLH(0x12>>1,LCD_REG12, LCD_REG13); /* mem adr. offset, screen 1 vsize(lsb)*/ \
        LCD_WRITE_REGLH(0x14>>1,LCD_REG14, 0);                                                   \
        LCD_WRITE_REGLH(0x18>>1,LCD_REG18, LCD_REG19);                                                   \
        LCD_WRITE_REGLH(0x1a>>1,0, LCD_REG1B);                                                   \
        LCD_WRITE_REGLH(0x1c>>1,LCD_REG1C, 0)

/*********************************************************************
*
*       ARM : Sharp LH79520, Logic PD board, QVGA display
*
**********************************************************************
*/

#elif defined TARGET_LH79520_QVGA

#define LCD_MEMBASE 0x21F6A000

#define LCD_BITSPERPIXEL   16
#define LCD_CONTROLLER   3200
#define LCD_XSIZE         240
#define LCD_YSIZE         320

#define LCD_SWAP_BYTE_ORDER (1)
#define LCD_SWAP_RB (0)
#define LCD_FIXEDPALETTE  555
#define LCD_ENDIAN_BIG 0
#define LCD_VRAM_ADR  LCD_MEMBASE

/* RESET, CLOCK AND POWER CONTROLLER */
#define __RCPCBASE  0xFFFE2000
#define __PERIPHCLKCTRL     *(volatile U32*)(__RCPCBASE + 0x0024)
#define __PERIPHCLKCTRL2    *(volatile U32*)(__RCPCBASE + 0x0028)
#define __PERPIHCLKSELECT	  *(volatile U32*)(__RCPCBASE + 0x0030)
#define __PERIPHCLKSELECT2	*(volatile U32*)(__RCPCBASE + 0x0034)
#define __LCDCLKPRESCALE	  *(volatile U32*)(__RCPCBASE + 0x0040)

/* COLOR LCD CONTROLLER */
#define __CLCDCBASE  0xFFFF4000
#define __LCDTIMING0    *(volatile U32*)(__CLCDCBASE + 0x0000)
#define __LCDTIMING1    *(volatile U32*)(__CLCDCBASE + 0x0004)
#define __LCDTIMING2    *(volatile U32*)(__CLCDCBASE + 0x0008)
#define __LCDUPBASE     *(volatile U32*)(__CLCDCBASE + 0x0010)
#define __LCDLPBASE	    *(volatile U32*)(__CLCDCBASE + 0x0014)
#define __LCDINTRENABLE *(volatile U32*)(__CLCDCBASE + 0x0018)
#define __LCDCONTROL    *(volatile U32*)(__CLCDCBASE + 0x001C)
#define __LCDSTATUS	    *(volatile U32*)(__CLCDCBASE + 0x0020)
#define __LCDINTERRUPT  *(volatile U32*)(__CLCDCBASE + 0x0024)
#define __LCDPALLETTE   *(volatile U32*)(__CLCDCBASE + 0x0200)
/* CLCDCBASE + 0x200 - 0x3FC LCDPALETTE 256