stv199.h

这是DVB tuner驱动部分和其它相关的源码和一些技术资料文档.

/*****************************************************************************
File Name   : stv199.h

Description : Low-level STV0199A access routines.

Copyright (C) 1999 STMicroelectronics

Reference   :

*****************************************************************************/

/* Define to prevent recursive inclusion */
#ifndef _STV0199A_H
#define _STV0199A_H

/* Includes --------------------------------------------------------------- */

/* Exported Constants ----------------------------------------------------- */

#define STV0199A_NO_ERROR               ST_NO_ERROR
#define STV0199A_ERROR_BAD_PARAMETER    ST_ERROR_BAD_PARAMETER

/* Maximum signal quality */
#define STV0199A_MAX_SIGNAL_QUALITY     100

/* Maximum signal quality */
#define STV0199A_MAX_BER                200000

/* Maximum attempts on an I2C failure */
#define STV0199A_I2C_RETRIES            5

/* Number of STV0199 register */
#define STV0199A_NUMBER_REGISTERS       46

/* Register reset settings */
#define STV0199A_RESET_SETTINGS \
{ \
    0x00,	0x1E,	0x14,	0x0F,	0x09,	0x05,	0x19,	0x00, \
    0x00,       0x1F,	0xBC,	0x92,	0x34,	0x00,	0xCC,	0x00, \
    0x00,	0x52,   0x01,	0x01,	0x00,	0xB4,	0x01,	0x80, \
    0x00,	0x02,	0x00,   0x00,	0x06,	0x00,	0x26,	0x00, \
    0x00,	0x00,	0x00,	0x00,   0x00,	0x00,	0x00,	0x00, \
    0x00,	0x00,	0x00,	0x00,	0x00,   0x00 \
}

/* STV0199A I2C register map */
#define STV0199A_CR1     (0x00)  /* input configuration, c */
#define STV0199A_VTH0    (0x01)  /* threshold registers, nc */
#define STV0199A_VTH1    (0x02)
#define STV0199A_VTH2    (0x03)
#define STV0199A_VTH3    (0x04)
#define STV0199A_VTH4    (0x05)
#define STV0199A_VSEARCH (0x06)  /* search, nc  */
#define STV0199A_VERROR  (0x07)  /* Bit Error Rate, nc */
#define STV0199A_VSTATUS (0x08)  /* status, CF, PRF, LK, nc */
#define STV0199A_VENRATE (0x09)  /* puncture rate enable, nc */
#define STV0199A_RS      (0x0A)  /* Reed Solomon control, c */
#define STV0199A_ID      (0x0B)  /* device identifier, value = 0x91 */
#define STV0199A_RTC     (0x0C)  /* timing constant, c */
#define STV0199A_RTF     (0x0D)  /* timing Frequency register, nc */
#define STV0199A_CLC     (0x0E)  /* carrier loop control parameters, c */
#define STV0199A_CLF     (0x0F)  /* Derotator integrator value, nc */
#define STV0199A_NU      (0x10)  /* Not used */
#define STV0199A_AGC     (0x11)  /* M factor of the AGC #1, c */
#define STV0199A_AGC1I   (0x12)  /* AGC #1 integrator value, c */
#define STV0199A_AGC1C   (0x13)  /* Tuner AGC #1 control, c */
#define STV0199A_ERRSYMB (0x14)  /* Carrier/Noise indicator, nc */
#define STV0199A_AGC2O   (0x15)  /* M factor & signal AGC #2 coeff, n */
#define STV0199A_AGC2G   (0x16)  /* AGC #2 integrator value, n */
#define STV0199A_SFRM    (0x17)  /* MSB of expected baud Freq, n */
#define STV0199A_SFRL    (0x18)  /* LSB of expected baud Freq, n */
#define STV0199A_ECOL    (0x19)  /* error monitoring reg */
#define STV0199A_ECNTM   (0x1A)  /* msb of error count */
#define STV0199A_ECNTL   (0x1B)  /* lsb of error count */
#define STV0199A_MCR     (0x1C)  /* A/D sampling clock Freq, max = 60MHz, n */
#define STV0199A_ACR     (0x1D)  /* Auxillary clock programmation, n */
#define STV0199A_F22FR   (0x1E)  /* F22 Frequency control for DISEQC, n */
#define STV0199A_F22CR   (0x1F)  /* F22 port control, n */

/* Property register/bitmask/sign definitions */

#define STV0199A_IQ_PROPERTY                { STV0199A_CR1, 0x01 }
#define STV0199A_ROLL_OFF_PROPERTY          { STV0199A_CR1, 0x02 }
#define STV0199A_H_PROPERTY                 { STV0199A_VSEARCH, 0x03 }
#define STV0199A_TO_PROPERTY                { STV0199A_VSEARCH, 0x0C }
#define STV0199A_SN_PROPERTY                { STV0199A_VSEARCH, 0x30 }
#define STV0199A_CF_PROPERTY                { STV0199A_VSTATUS, 0x80 }
#define STV0199A_LK_PROPERTY                { STV0199A_VSTATUS, 0x08 }
#define STV0199A_E_PROPERTY                 { STV0199A_VENRATE, 0x1F }
#define STV0199A_ALPHA_TIMING_PROPERTY      { STV0199A_RTC, 0x70 }
#define STV0199A_BETA_TIMING_PROPERTY       { STV0199A_RTC, 0x07 }
#define STV0199A_TLOOP_FREQUENCY_PROPERTY   { STV0199A_RTF, 0xFF }
#define STV0199A_BETA_CARRIER_PROPERTY      { STV0199A_CLC, 0x07 }
#define STV0199A_ALGORITHM_PROPERTY         { STV0199A_CLC, 0x08 }
#define STV0199A_ALPHA_CARRIER_PROPERTY     { STV0199A_CLC, 0x70 }
#define STV0199A_CLOOP_FREQUENCY_PROPERTY   { STV0199A_CLF, 0xFF }
#define STV0199A_AGC1_OPEN_DRAIN_PROPERTY   { STV0199A_AGC, 0x40 }
#define STV0199A_AGC1_REF_PROPERTY          { STV0199A_AGC, 0x3F }
#define STV0199A_AGC1_INTEGRATOR_PROPERTY   { STV0199A_AGC1I, 0xFF }
#define STV0199A_BETA_AGC1_PROPERTY         { STV0199A_AGC1C, 0x07 }
#define STV0199A_AGC2_COEFFICIENT_PROPERTY  { STV0199A_AGC2O, 0x60 }
#define STV0199A_AGC2_REF_PROPERTY          { STV0199A_AGC2O, 0x1F }
#define STV0199A_AGC2_GAIN_PROPERTY         { STV0199A_AGC2G, 0xFF }
#define STV0199A_SYMBOL_MSB_PROPERTY        { STV0199A_SFRM, 0xFF }
#define STV0199A_SYMBOL_LSB_PROPERTY        { STV0199A_SFRL, 0xFF }
#define STV0199A_M_DIVISOR_PROPERTY         { STV0199A_MCR, 0x07 }
#define STV0199A_DIR_CLOCK_PROPERTY         { STV0199A_MCR, 0x08 }
#define STV0199A_P_DIVISOR_PROPERTY         { STV0199A_MCR, 0x70 }
#define STV0199A_AUX_ENA_PROPERTY           { STV0199A_ACR, 0x20 }
#define STV0199A_P_AUX_PROPERTY             { STV0199A_ACR, 0x10 }
#define STV0199A_PUNCTURE_RATE_PROPERTY     { STV0199A_VSTATUS, 0x07 }
#define STV0199A_TS_OUTPUT_MODE_PROPERTY    { STV0199A_CR1, 0x10 }
#define STV0199A_OUTPUT_CLOCK_CFG_PROPERTY  { STV0199A_RS, 0x01 }
#define STV0199A_OUTPUT_CLOCK_PLR_PROPERTY  { STV0199A_RS, 0x02 }

/* REGISTER BIT ASSIGNMENTS */
/* STV0199A Register CR1 (0x00) Input configuration */
#define STV0199A_CR1_IQ_MSK      (0x01)  /* I/Q or (low) Q/I. 1 = -Q, 0 = Q */
#define STV0199A_CR1_IQ_SFT      (0)     /* Number of shifts to bit pos. 0 */
#define STV0199A_CR1_ROLLOFF_MSK (0x02)  /* Roll-off Factor 1 = 20%, 0 = 35%*/
#define STV0199A_CR1_ROLLOFF_SFT (1)     /* Number of shifts to bit pos. 0 */
#define STV0199A_CR1_BPSK_MSK    (0x08)  /* BPSK /QPSK */
#define STV0199A_CR1_BPSK_SFT    (3)     /* Number of shifts to bit pos. 0 */
#define STV0199A_CR1_SERIAL_MSK  (0x10)  /* Serial /Parallel */
#define STV0199A_CR1_SERIAL_SFT  (4)     /* Number of shifts to bit pos. 0 */
#define STV0199A_CR1_HIGHZ_MSK   (0x20)  /* High-Z /Normal outputs */
#define STV0199A_CR1_HIGHZ_SFT   (5)     /* Number of shifts to bit pos. 0 */

/* STV0199A Register VTH0 (0x01) Threshold registers */
#define STV0199A_VTH0_MSK        (0x7F)  /* Threshold value for rate 1/2 */
#define STV0199A_VTH0_SFT        (0)     /* Number of shifts to bit pos. 0 */

/* STV0199A Register VTH1 (0x02) */
#define STV0199A_VTH1_MSK        (0x7F)  /* Threshold value for rate 2/3 */
#define STV0199A_VTH1_SFT        (0)     /* Number of shifts to bit pos. 0 */

/* STV0199A Register VTH2 (0x03) */
#define STV0199A_VTH2_MSK        (0x7F)  /* Threshold value for rate 3/4 */
#define STV0199A_VTH2_SFT        (0)     /* Number of shifts to bit pos. 0 */

/* STV0199A Register VTH3 (0x04) */
#define STV0199A_VTH3_MSK        (0x7F)  /* Threshold value for rate 5/6 */
#define STV0199A_VTH3_SFT        (0)     /* Number of shifts to bit pos. 0 */

/* STV0199A Register VTH4 (0x05) */
#define STV0199A_VTH4_MSK        (0x7F)  /* Threshold value for rate 6/7 or 7/8 */
#define STV0199A_VTH4_SFT        (0)     /* Number of shifts to bit pos. 0 */

/* STV0199A Register VSEARCH (0x06) Search  */
#define STV0199A_VSEARCH_H_MSK   (0x03)  /* Hysteresis value */
#define STV0199A_VSEARCH_H_SFT   (0)     /* Number of shifts to bit pos. 0 */
#define STV0199A_VSEARCH_TO_MSK  (0x0C)  /* Timeout value */
#define STV0199A_VSEARCH_TO_SFT  (2)     /* Number of shifts to bit pos. 0 */
#define STV0199A_VSEARCH_SN_MSK  (0x30)  /* AVeraging period */
#define STV0199A_VSEARCH_SN_SFT  (4)     /* Number of shifts to bit pos. 0 */
#define STV0199A_VSEARCH_FRZE_MSK (0x40) /* Freeze */
#define STV0199A_VSEARCH_FRZE_SFT (6)    /* Number of shifts to bit pos. 0 */
#define STV0199A_VSEARCH_AUTO_MSK (0x80) /* Automatic /manual */
#define STV0199A_VSEARCH_AUTO_SFT (7)    /* Number of shifts to bit pos. 0 */

/* STV0199A Register VERROR (0x07) Bit Error Rate */
#define STV0199A_VERROR_MSK      (0xFF)  /* Bit Error Rate */
#define STV0199A_VERROR_SFT      (0)     /* Number of shifts to bit pos. 0 */

/* STV0199A Register VSTATUS (0x08) Status, CF, PRF, LK */
#define STV0199A_VSTATUS_PR_MSK  (0x07)  /* Current Puncture Rate */
#define STV0199A_VSTATUS_PR_SFT  (0)     /* Number of shifts to bit pos. 0 */
#define STV0199A_VSTATUS_PR_1_2  (4)     /* Basic 1/2 */
#define STV0199A_VSTATUS_PR_2_3  (0)     /* Punctured 2/3 */
#define STV0199A_VSTATUS_PR_3_4  (1)     /* Punctured 3/4 */
#define STV0199A_VSTATUS_PR_5_6  (2)     /* Punctured 5/6 */
#define STV0199A_VSTATUS_PR_7_8  (3)     /* Punctured 7/8 (Mode A) or 6/7 (Mode B) */
#define STV0199A_VSTATUS_LK_MSK  (0x08)  /* 1 = Locked, 0 = searching */
#define STV0199A_VSTATUS_LK_SFT  (3)     /* Number of shifts to bit pos. 0 */
#define STV0199A_VSTATUS_PRF_MSK (0x10)  /* Puncture Rate Found */
#define STV0199A_VSTATUS_PRF_SFT (4)     /* Number of shifts to bit pos. 0 */
#define STV0199A_VSTATUS_IP_MSK  (0x20)  /* ?? */
#define STV0199A_VSTATUS_IP_SFT  (5)     /* Number of shifts to bit pos. 0 */
#define STV0199A_VSTATUS_CF_MSK  (0x80)  /* Carrier Found */
#define STV0199A_VSTATUS_CF_SFT  (7)     /* Number of shifts to bit pos. 0 */

/* STV0199A Register VENRATE (0x09) Puncture rate enable */
#define STV0199A_VENRATE_E0_MSK  (0x01)  /* Enable Basic Puncture Rate 1/2 */
#define STV0199A_VENRATE_E0_SFT  (0)     /* Number of shifts to bit pos. 0 */
#define STV0199A_VENRATE_E1_MSK  (0x02)  /* Enable Puncture Rate 2/3 */
#define STV0199A_VENRATE_E1_SFT  (1)     /* Number of shifts to bit pos. 0 */
#define STV0199A_VENRATE_E2_MSK  (0x04)  /* Enable Puncture Rate 3/4 */
#define STV0199A_VENRATE_E2_SFT  (2)     /* Number of shifts to bit pos. 0 */
#define STV0199A_VENRATE_E3_MSK  (0x08)  /* Enable Puncture Rate 5/6 */
#define STV0199A_VENRATE_E3_SFT  (3)     /* Number of shifts to bit pos. 0 */
#define STV0199A_VENRATE_E4_MSK  (0x10)  /* Enable Puncture Rate 6/7 Mode B
                                            or 7/8 Mode A*/
#define STV0199A_VENRATE_E4_SFT  (4)     /* Number of shifts to bit pos. 0 */
#define STV0199A_VENRATE_SYD_MSK (0x08)  /* Disable Synchro Research */
#define STV0199A_VENRATE_SYD_SFT (7)     /* Number of shifts to bit pos. 0 */

/* STV0199A Register RS (0x0A) Reed Solomon control */
#define STV0199A_RS_RS0_MSK      (0x01)  /* 1 = CK_OUT remains low during
                                       parity bits, 0 = CK_OUT is continuous */
#define STV0199A_RS_RS0_SFT      (0)     /* Number of shifts to bit pos. 0 */
#define STV0199A_RS_RS1_MSK      (0x02)  /* Output Clock Polarity, data & ctrl
                                           signals change: 1 = during H->L
                                           of CK_OUT, 0 = during L->H */
#define STV0199A_RS_RS1_SFT      (1)     /* Number of shifts to bit pos. 0 */
#define STV0199A_RS_RS2_MSK      (0x04)  /* Super Synchro Suppression
                                           1 = all sync bytes are 0x47,
                                    0 = sync is complemented eVery 8th byte */
#define STV0199A_RS_RS2_SFT      (2)     /* Number of shifts to bit pos. 0 */
#define STV0199A_RS_RS3_MSK      (0x08)  /*  */
#define STV0199A_RS_RS3_SFT      (3)     /* Number of shifts to bit pos. 0 */
#define STV0199A_RS_RS4_MSK      (0x10)  /*  */
#define STV0199A_RS_RS4_SFT      (4)     /* Number of shifts to bit pos. 0 */
#define STV0199A_RS_RS5_MSK      (0x20)  /*  */
#define STV0199A_RS_RS5_SFT      (5)     /* Number of shifts to bit pos. 0 */
#define STV0199A_RS_RS6_MSK      (0x40)  /*  */
#define STV0199A_RS_RS6_SFT      (6)     /* Number of shifts to bit pos. 0 */
#define STV0199A_RS_RS7_MSK      (0x80)  /*  */
#define STV0199A_RS_RS7_SFT      (7)     /* Number of shifts to bit pos. 0 */

/* STV0199A Register ID (0x0B) Device identifier, value = 0x91 */
#define STV0199A_ID_MSK          (0xFF)  /* device identifier, value = 0x91 */
#define STV0199A_ID_SFT          (0)     /* Number of shifts to bit pos. 0 */

/* STV0199A Register RTC (0x0C) Timing constant */
#define STV0199A_RTC_BETA_MSK    (0x07)  /* Beta timing constant */
#define STV0199A_RTC_BETA_SFT    (0)     /* Number of shifts to bit pos. 0 */
#define STV0199A_RTC_APLHA_MSK   (0x70)  /* Alpha timing constant */
#define STV0199A_RTC_ALPHA_SFT   (4)     /* Number of shifts to bit pos. 0 */

/* STV0199A Register RTF (0x0D) Timing Frequency register */
#define STV0199A_RTF_MSK         (0xFF)  /* Timing Frequency register */
#define STV0199A_RTF_SFT         (0)     /* Number of shifts to bit pos. 0 */

/* STV0199A Register CLC (0x0E) Carrier loop control parameters */
#define STV0199A_CLC_BETA_MSK    (0x07)  /* Carrier Loop Control Beta Carrier */
#define STV0199A_CLC_BETA_SFT    (0)     /* Number of shifts to bit pos. 0 */
#define STV0199A_CLC_ALG_MSK     (0x08)  /* Carrier Loop Control Algorithm */
#define STV0199A_CLC_ALG_SFT     (3)     /* Number of shifts to bit pos. 0 */
#define STV0199A_CLC_ALPHA_MSK   (0x70)  /* Carrier Loop Control Alpha Carrier */
#define STV0199A_CLC_ALPHA_SFT   (4)     /* Number of shifts to bit pos. 0 */
#define STV0199A_CLC_DEROT_MSK   (0x80)  /* Carrier Loop Derotator On /Off */
#define STV0199A_CLC_DEROT_SFT   (7)     /* Number of shifts to bit pos. 0 */

/* STV0199A Register CLF (0x0F) Derotator integrator value */
#define STV0199A_CLF_MSK         (0xFF)  /* Derotator integrator value */
#define STV0199A_CLF_SFT         (0)     /* Number of shifts to bit pos. 0 */

/* STV0199A Register NU (0x10) Not used */

/* STV0199A Register AGC (0x11) M factor of the AGC #1 */
#define STV0199A_AGC_M1_MSK      (0x3F)  /* M factor of the AGC #1 */
#define STV0199A_AGC_M1_SFT      (0)     /* Number of shifts to bit pos. 0 */
#define STV0199A_AGC_OD_MSK      (0x40)  /* 1 = Open Drain, 0 = normal */
#define STV0199A_AGC_OD_SFT      (6)     /* Number of shifts to bit pos. 0 */
#define STV0199A_AGC_LAGC_MSK    (0x80)  /* LAGC 1 = inVerted, 0 = normal */
#define STV0199A_AGC_LAGC_SFT    (7)     /* Number of shifts to bit pos. 0 */

/* STV0199A Register AGC1I (0x12) AGC #1 integrator value */
#define STV0199A_AGC1I_MSK       (0xFF)  /* AGC #1 integrator value */
#define STV0199A_AGC1I_SFT       (0)     /* Number of shifts to bit pos. 0 */
#define STV0199A_AGC1I_MAX       (255)   /* Maximum value of AGC */