mst7x.c

MST720-DEMO程序

/******************************************************************************
 Copyright (c) 2005 MStar Semiconductor, Inc.
 All rights reserved.

 [Module Name]: Mst7xxx.c
 [Date]:	17-Jan-2005
 [Comment]:
   Functions For Mst7xxx IC.
 [Reversion History]:
*******************************************************************************/
#define _MST7X_C_

/********************
* INCLUDE FILES     *
*********************/
#include "Project.h"
#include "Mcu_reg.h"
#include "TypeDef.h"
#include "msACE.h"
#include "Ms_RWreg.h"
#include "Ms7X_reg.h"
#include "Mst7x.h"
#include "Ms_Func.h"
#include "Debug.h"
#include "Misc.h"
#include "PANEL.h"
#include "OSDFunc.h"
#include "Global.h"

/********************
* STATIC DATA	    *
*********************/
BYTE code tMST7xInitialize[]=
{
// select register bank scaler (BANK0)
//===============================================================
	1, GEN_00_REGBK,				
	REGBANKSCALER,				// 00h

	4, BK0_01_DBFC,
	0x00, 0x0C, 0x00, 0x10,			// BK0_01_DBFC, BK0_02_ISELECT, BK0_03_IPCTRL2, BK0_04_ISCTRL
	
#if PANEL_TYPE_SEL == PNL_AU20_D
	0x04, BK0_0D_LYL,
	0x04, 0x00, 0x20, 0x20,			// BK0_0D_LYL, BK0_0E_INTLX, BK0_0F_ASCTRL, BK0_10_COCTRL1
#elif ((PANEL_TYPE_SEL == PNL_AU07_AT)||(PANEL_TYPE_SEL == PNL_LG07_AT)||(PANEL_TYPE_SEL == PNL_TMD08_AT)||(PANEL_TYPE_SEL == PNL_PVI09_AT)||(PANEL_TYPE_SEL == PNL_AU85_AT))//kevin
	0x04, BK0_0D_LYL,
	0x04, 0x00, 0x10, 0xA0,			// BK0_0D_LYL, BK0_0E_INTLX, BK0_0F_ASCTRL, BK0_10_COCTRL1
#else
	0x04, BK0_0D_LYL,
	0x00, 0x00, 0x10, 0x20,			// BK0_0D_LYL, BK0_0E_INTLX, BK0_0F_ASCTRL, BK0_10_COCTRL1
#endif

#if ((MARIA_TYPE_SEL == MARIA_2) && ENABLE_VD_DSP)
	1, BK0_0E_INTLX,
	0x80,

	// 1, BK0_1D_INTENC,
	// 0x40,
#endif

	// Interrupt setting
	0x02, BK0_16_INTCTROL,
	0x00, 0x0F,				// BK0_16_INTCTROL, BK0_17_INTPULSE
	
	0x01, BK0_1F_INTEND,
	0x40,					// BK0_1F_INTEND

	// MPLL setting 216Mhz
	0x01, BK0_22_MPL_M,
	0x72,					// BK0_22_MPL_M

#if SSC_ENABLE
	#if(MARIA_TYPE_SEL == MARIA_2)
		0x02, BK0_23_OPL_CTL0,
		0x40, 0x03,
		#if(PANEL_TYPE_SEL == PANEL_LVDS)
			0x02, BK0_2D_OPL_TSTA0,
			0x00, 0x00,
		#else
			0x02, BK0_2D_OPL_TSTA0,
			0x00, 0x05,
		#endif
	#else
		0x01, BK0_23_OPL_CTL0,
		0x40,					// BK0_23_OPL_CTL0
	#endif
	
	0x04, BK0_28_OPL_STEP0,				
	DEF_SSC_STEP0, DEF_SSC_STEP1,		// BK0_28_OPL_STEP0, BK0_29_OPL_STEP1
	DEF_SSC_SPAN0, DEF_SSC_SPAN1,		// BK0_2A_OPL_SPAN0, BK0_2B_OPL_SPAN1
	
#else
	#if(MARIA_TYPE_SEL == MARIA_2)
		0x02, BK0_23_OPL_CTL0,
		0x00, 0x07,
		#if(PANEL_TYPE_SEL == PANEL_LVDS)
			0x02, BK0_2D_OPL_TSTA0,
			0x00, 0x00,
		#else
			0x02, BK0_2D_OPL_TSTA0,
			0x00, 0x05,
		#endif
	#else
		0x01, BK0_23_OPL_CTL0,
		0x00,					// BK0_23_OPL_CTL0
	#endif
#endif

	0x01, BK0_57_OSCTRL1,
	0x42,					// BK0_57_OSCTRL1

	0x02, BK0_5C_FRAME_COLOR_1,		// Set frame color and enable
	0x3F, 0x00,				// BK0_5C_FRAME_COLOR_1, BK0_5D_FRAME_COLOR_2

	0x12, BK0_64_CM11_L,			// 3X3 color matrix
	0x3B, 0x06, 0x18, 0x05, 0x00, 0x00,		// BK0_64, BK0_65, BK0_66, BK0_67, BK0_68, BK0_69
	0x2C, 0x13, 0x18, 0x05, 0x87, 0x11,		// BK0_6A, BK0_6B, BK0_6C, BK0_6D, BK0_6E, BK0_6F
	0x00, 0x00, 0x18, 0x05, 0xE1, 0x07,		// BK0_70, BK0_71, BK0_7h, BK0_73, BK0_74, BK0_75

#if ((BOARD_TYPE_SEL == BD_DEMO_7985M_IDP)||(BOARD_TYPE_SEL == BD_SOCKET_7985M_IDP)||(BOARD_TYPE_SEL == BD_SOCKET_7915MA_IDP))
	1, BK0_87_DEBUG,				// Select PWM1/2 output 
	0x0A,					// BK0_87_DEBUG
#else
	1, BK0_87_DEBUG,				// Select PWM1/2 output 
	0x08,					// BK0_87_DEBUG
#endif

	2, BK0_CB_ATOCTRL,
	0x01, 0x40,				// BK0_CB_ATOCTRL, BK0_CC_AOVDV
	
	2, BK0_E4_ISOVRD,
	0x00, 0x00,				// BK0_E4_ISOVRD, BK0_E5_MDCTRL

	0x02, BK0_E8_HSTOL,			// Set Hsync and Vsync tolerance
	0x05, 0x01,				// BK0_E8_HSTOL, BK0_E9_VSTOL

#if(MARIA_TYPE_SEL == MARIA_2)
	0x01, BK0_F7_TEST_BUS_SELECT,
	0x08,
#endif
			
	0x01, BK0_F8_TEST_MODE, 		// Disable test mode
	0x00,					// BK0_F8_TEST_MODE

// select register bank adc (BANK1)
//===============================================================
	1, GEN_00_REGBK,				
	REGBANKADC,				// 00h

	1, BK1_0C_GCTRL,				// For YPbPr and VGA Hync input polarity
	0x02,					// BK1_0C_GCTRL

#if FSC_8X
	1, BK1_16_DITHCTRL,
	0x70,					// BK1_16_DITHCTRL
#endif	// FSC_8X

	1, BK1_2C_RGB_BW_SEL1,			// iClamp (20050614 update)
	0xF0,					// BK1_2C_RGB_BW_SEL1

	1, BK1_33,				// SOG filter bandwidth
	0x18,					// BK1_33

	1, BK1_35,				// for SOG threshold (recommend value) 
	0x08,					// BK1_35

	1, BK1_3E,				// ??
	0x82,					// BK1_3E

	1, BK1_49,
	0x0C,					// BK1_49  0x0F   // Forte0714 ON/OFF BUCK current sense.

	1, BK1_4E,
	0xF9,					// BK1_4E  0x59   // Forte0714 increase reference current for BUCK current sense.

	10, BK1_90_SARADC_CTRL,			// SAR Key setting
	0x20, 0x20, 0x07, 0x00,		//0X07-0X00	// BK1_90_SARADC_CTRL, BK1_91_SARADC_SAMPRD, BK1_92_SARADC_AISEL, BK1_93_SARADC_TEST
	0x3F, 0x05, 0x3F, 0x00,			// BK1_94_SAR_CH1_UPB, BK1_95_SAR_CH1_LOB, BK1_96_SAR_CH2_UPB, BK1_97_SAR_CH2_LOB
	0x3F, 0x00,				// BK1_98_SAR_CH3_UPB, BK1_99_SAR_CH3_LOB

#if ((MARIA_TYPE_SEL == MARIA_2) && PANEL_LVDS)
	1, BK1_AC_EN_CDAC,
	0x01,
#endif

#if ((BOARD_TYPE_SEL == BD_DEMO_7985M_IDP)||(BOARD_TYPE_SEL == BD_SOCKET_7985M_IDP)||(BOARD_TYPE_SEL == BD_SOCKET_7915MA_IDP))
	1, BK1_F3_PWMCLK,				// For Backlight control
	0x18,					// BK1_F3_PWMCLK
#endif

	1, BK1_F4_PWM1C,
	SET_BACKLIGHT_PWM,			// BK1_F4_PWM1C

	2, BK1_F6_PWM1EPL,
	0x00, 0x01,				// BK1_F6_PWM1EPL, BK1_F7_PWM1EPH

// select register bank VFE (BANK2)
//===============================================================
	1, GEN_00_REGBK,			
	REGBANKVFE,				// 00h

#if(MARIA_TYPE_SEL == MARIA_2)
	1, BK2_17_FSC_SEL,
	0xF9,

	1, BK2_19_MVDET_EN,
	0xC2,							// For SECAM input

	1, BK2_26_APL_K1_NORMAL,
	0x30,
	
	1, BK2_27_APL_K2_NORMAL,		// ?? (20050609)
	0x08,

	1, BK2_4A_AGC_LOWTH,			// 20051124 Antony
	0xFF,							// BK2_4A_AGC_LOWTH

	1, BK2_62,						// 20051124 Antony
	0x10,							// BK2_62

	1, BK2_6A_VCR_DETECT1,			// 20051115.Eric.Lin: Force VCR mode
	0x51,//0xD1,							// BK2_6A_VCR_DETECT1

	1, BK2_6F,
	0x81,

	1, BK2_67_WP_REDO,
	0x07,

	1, BK2_23_APLL_TRANGE, 
	0x80,
	
	1, BK2_76_656_CTRL1,				// For Mode1, enable 656 mode (20050722)
	0x04,							// BK2_76_656_CTRL1

	1, BK2_7B_656_HDEW,				// 656_HDEW
	0x00,							//BK2_7B_656_HDEW
	
	1, BK2_7F,
	0x63,

	1, BK2_8F_FSC_TABLE,
	0x19,
	
#if ((MARIA_TYPE_SEL == MARIA_2) && ENABLE_VD_DSP)
	1, BK2_BB,
	0x00,
#else
	1, BK2_BB,
	0x04,
#endif

#else	// MARIA 1
	1, BK2_0F,				// ??
	0x80,					// BK2_0F
	
#if FSC_8X
	1, BK2_1A_SVD_EN,			// Enable bit0 for video decoder double DE ouput 
	0x07,					// BK2_1A_SVD_EN (20050721)
#endif	// FSC_8X

	1, BK2_1D_VCR_VLSHT,			// improve VCR compatibility (20050721)
	//0x00,					// BK2_1D_VCR_VLSHT
	0x0F,	//20050921 (0x00~0x20) improve VCR compatibilit

	2, BK2_21_APLL_CTRL2,			// ?? (20050609)
	0x19, 0xC6,				// BK2_21_APLL_CTRL2, BK2_22_APLL_CTRL3

	2, BK2_26_APL_K1_NORMAL,		// ?? (20050609)
	0x30, 0x02,					// BK2_26_APL_K1_NORMAL, BK2_27_APL_K2_NORMAL
	
	1, BK2_2F_BLACK_SEL,			// Force no setup for black level (2Fh[7:6] = 2b'10)
	0x81,					// BK2_2F_BLACK_SEL

	1, BK2_40_PGA_CTRL1,			// 20050518 DavidKao for MariaC: 0xC3 => 0x43
	0x43,					// BK2_40_PGA_CTRL1

	4, BK2_43_AGC_CTRL1,			// AGC setting
	0x94, 0xF0, 0x4E, 0x78,			// BK2_43_AGC_CTRL1, BK2_44_AGC_FINE, BK2_45_AGC_CTRL2, BK2_46_AGC_K_CTRL

	1, BK2_4A_AGC_LOWTH,
	0xFF,					// BK2_4A_AGC_LOWTH

	1, BK2_52_COMB_LL_CTRL,			// ?? (20050617)
	0xE2,					// BK2_52_COMB_LL_CTRL

	3, BK2_5D_ACC_CRTL,			// ACC setting
	0x48, 0x24, 0x08,				// BK2_5D_ACC_CRTL, BK2_5E_ACC_GAIN, BK2_5F

	1, BK2_65_AGC_CTRL4,			// more stable for some gray bar pattern (20050721)
	0x54,					// BK2_65_AGC_CTRL4

	1, BK2_69_SRC_CTRL1,			// Select 2D-COMB input
	0x82,					// BK2_69_SRC_CTRL1

	1, BK2_75,				// For black level setting
	0x40,					// BK2_75

	1, BK2_77,				// Reduce 656 blank area pixel number (20050721)
	0x03,					// BK2_77

	1, BK2_A4_DPL_K1_VCR,			// improve VCR compatibility (20050721)
	0x30,					// BK2_A4_DPL_K1_VCR

	1, BK2_A6_DPL_K1_VCR_V,			// improve VCR compatibility (20050721)
	0x38,					// BK2_A6_DPL_K1_VCR_V

	1, BK2_AC,				// improve VCR compatibility (20050721)
	0x88,					// BK2_AC

#if DEMODULELATOR_MODE

	1, BK2_76_656_CTRL1,			// For Mode1, enable 656 mode (20050722)
	0x02,					// BK2_76_656_CTRL1

	1, BK2_7A_656_HDES2,			// For black level setting
	0x3C,					//BK2_7A_656_HDES2

	1, BK2_7B_656_HDEW,			// 656_HDEW
	0xCC,					// BK2_7B_656_HDEW

	1, BK2_7E_656_CTRL2,			// For black level setting
	0x90,					//BK2_7E_656_CTRL2

	2, BK2_9D_DPL_NSPL_HIGH,			// Mode1 Scaling H size.  (20050722)
	0x6C, 0x00,				// BK2_9D_DPL_NSPL_HIGH, BK2_9E_DPL_NSPL_LOW

	1, BK2_A1_DPL_K2_FORCE, 			// DPL_K2_FORCE For 1:1 Scaling at Mode1
	0x60,					// BK2_A1_DPL_K2_FORCE


#endif	//DEMODULELATOR_MODE

#if FSC_8X
	1, BK2_68_CLK_CTRL1,			// CLK_CTRL1
	0xDD,					// BK2_68_CLK_CTRL1

	1, BK2_8F_FSC_TABLE,			// FSC_TABLE
	0x19,					//BK2_8F_FSC_TABLE

#else	// FSC_8X
	1, BK2_68_CLK_CTRL1,			// CLK_CTRL1
	0x04,					// BK2_68_CLK_CTRL1

	1, BK2_7B_656_HDEW,			// 656_HDEW
	0xB3,					//BK2_7B_656_HDEW

	1, BK2_8F_FSC_TABLE,			// FSC_TABLE
	0x18,					// BK2_8F_FSC_TABLE

	1, BK2_9D_DPL_NSPL_HIGH,			// DPL_NSPL_HIGH
	0x6C,					// BK2_9D_DPL_NSPL_HIGH