sync.c

MST720-DEMO程序

		}
		if((ucTempBK3_72 & 0xF0) == 0)
		{
			ucSyncStatus |= SYNC_LOSS_MASK;
		}
		
		if(ucTempBK3_72 != g_ucVDStatus)
		{
			ucSyncStatus |= SYNC_LOSS_MASK;
			g_ucVDStatus = ucTempBK3_72;
		}
		mstWriteByte(GEN_00_REGBK, REGBANKSCALER);		// Switch bank0 Scaler
		//if(ucSyncStatus & SYNC_LOSS_MASK)
			//mstResetVedioDecoder();
	}
		
#endif

	mstWriteByte(BK0_18_INTSTA, 0x00);			// 20050809 Antony

	uwHFreq = mstReadWord(BK0_EB_HSPRD_H) & 0x1FFF;	// Get H Period count
	if ((uwHFreq == 0x1FFF) || (uwHFreq < 10))		
		ucSyncStatus |= NO_HSYNC_B;
	
	uwVFreq = mstReadWord(BK0_ED_VTOTAL_H) & 0x7FF;		// Get V period count
	if ((uwVFreq == 0x7FF) || (uwVFreq < 10))
		ucSyncStatus |= NO_VSYNC_B;

	ucSyncTemp = mstReadByte(BK0_EF_STATUS2);		// Get SYNC status

	ucSyncStatus |= (ucSyncTemp & (PAL_MODE_B+CSYNC_MODE_B+INTERLANCE_MODE_B+HSYNC_NEGATIVE_B+VSYNC_NEGATIVE_B));

#if !DEMODULELATOR_MODE
	mstWriteByte(GEN_00_REGBK, REGBANKVCF);		// Switch bank3 VCF
	
	mstWriteByte(BK3_70_COMB_STSA, 0xFF);			// clear CF status

	mstWriteByte(GEN_00_REGBK, REGBANKSCALER);		// Switch bank0 Scaler
#endif	//DEMODULELATOR_MODE

	miscDelay1ms(30);

	ucSyncTemp = mstReadByte(BK0_EF_STATUS2);

	if ((ucSyncStatus&(HSYNC_NEGATIVE_B+VSYNC_NEGATIVE_B)) != (ucSyncTemp&(HSYNC_NEGATIVE_B+VSYNC_NEGATIVE_B)))
		ucSyncStatus |= SYNC_LOSS_MASK;
	#if 0 //RS232DBG
		sysWriteString("sd1: ");
		sysWriteHex(ucSyncStatus, 1);
		sysWriteString(tChangeLine);
	#endif	//RS232DBG

	if (!g_bVCRMode)
	{

		if (!g_bAllOddFiled)
		{
			uwFreqTemp = mstReadWord(BK0_EB_HSPRD_H) & 0x1FFF;

			if (((uwHFreq-uwFreqTemp)>4)||((uwFreqTemp-uwHFreq)>4))
				ucSyncStatus |= SYNC_LOSS_MASK;

		}

		uwFreqTemp = mstReadWord(BK0_ED_VTOTAL_H) & 0x7FF;

		if (((uwVFreq-uwFreqTemp)>2)||((uwFreqTemp-uwVFreq)>2))
			ucSyncStatus |= SYNC_LOSS_MASK;

	}
	
	#if 0 //RS232DBG
		sysWriteString("sd2: ");
		sysWriteHex(ucSyncStatus, 1);
		sysWriteString(tChangeLine);
	#endif	//RS232DBG

	if (tOSDSourcSELSequence[Display.ucSourceSEL] <= SVIDEO2)
	{
		//if((mstReadByte(BK0_18_INTSTA) & 0x0D) != 0)	// 20050809 Antony
		if((mstReadByte(BK0_18_INTSTA) & 0x0C) != 0)	// 20050905
			ucSyncStatus |= SYNC_LOSS_MASK;
	}
	#if 0 //RS232DBG
		sysWriteString("sd4: ");
		sysWriteHex(ucSyncStatus, 1);
		sysWriteString(tChangeLine);
	#endif	//RS232DBG
	
#if !DEMODULELATOR_MODE
	if (tOSDSourcSELSequence[Display.ucSourceSEL] <= SVIDEO2)
	{
		mstWriteByte(GEN_00_REGBK, REGBANKVCF);	// Switch bank3 VCF
		
		ucSyncTemp = mstReadByte(BK3_70_COMB_STSA);
		
		if ((ucSyncTemp & 0x0D) != 0)		// check bit3,2,0 for no signal input
		{
			ucSyncStatus |= SYNC_LOSS_MASK;
		}
		else
		{
			ucSyncTemp = mstReadByte(BK3_72_COMB_STSC) & 0x07;	// Check BK3.72h[2:0]
			if(ucSyncTemp == 0x01)				// If video mode is NTSC(443)
			{
				//mstWriteByte(GEN_00_REGBK, REGBANKVFE);	// Switch to Bank2 VFE
				//ucSyncTemp = mstReadByte(0x02) & 0x03;	// Check BK2.02h[1:0]
				//if(ucSyncTemp == 0x02)			// If TV system is PAL
					ucSyncStatus |= DEMODULATION_MODE1_B;
			}
		}
		mstWriteByte(GEN_00_REGBK, REGBANKSCALER);	// Switch bank0 Scaler
	}
#endif	// !DEMODULELATOR_MODE

#if ((MARIA_TYPE_SEL == MARIA_2) && ENABLE_NEW_SYNC)
		mstWriteByte(GEN_00_REGBK, ucBank);
#endif


	return ucSyncStatus;

}

void mstSyncChangeHandler(void)
{
	BYTE ucTemp;

	//mstPatchFullOddField();//keivn for full odd field

	if ((g_ucSystemFlag&INPUT_TIMING_CHANGE_FLAG) == 0)	// If timing no chang than return
		return;

#if (MARIA_TYPE_SEL == MARIA_1)
	mstWriteByte(GEN_00_REGBK, REGBANKVFE); 	//Switch bank2 VFE
	mstWriteByte(BK2_4D_BRST_WINDOW2, 0x40);	// (20050609)
	mstWriteByte(GEN_00_REGBK, REGBANKSCALER);	//Switch bank0 Scaler

	ucTemp = mstReadByte(BK0_57_OSCTRL1);		// 20050812 Antony
	ucTemp &= ~_BIT0;				// clear BIT0
	ucTemp |= _BIT1;					// Set BIT1
	mstWriteByte(BK0_57_OSCTRL1, ucTemp);		// 20050812 Antony
#endif

#if 0 //((MARIA_TYPE_SEL == MARIA_2) && (PANEL_WIDTH > 720))
	if ((tOSDSourcSELSequence[Display.ucSourceSEL] <= SVIDEO2))
	{
		mstWriteByte(GEN_00_REGBK, REGBANKVFE); 	//Switch bank2 VFE
		mstWriteByte(BK2_7B_656_HDEW, 0xE0);
		mstWriteByte(GEN_00_REGBK, REGBANKSCALER);	//Switch bank0 Scaler
	}
#endif

	ucTemp = mstReadByte(BK0_1E_INTSTD);

#if((MARIA_TYPE_SEL == MARIA_2) && ENABLE_NEW_SYNC)
	if (((ucTemp & 0x1F) != 0)) //&&  (tOSDSourcSELSequence[Display.ucSourceSEL] > SVIDEO2))
#else
	if ((ucTemp & 0x1F) != 0) 
#endif
	{
		// 20050722 added by Antony for VCR mode detect
	#if (MARIA_TYPE_SEL == MARIA_1)
		if ((tOSDSourcSELSequence[Display.ucSourceSEL] <= SVIDEO2))
		{
			mstWriteByte(GEN_00_REGBK, REGBANKVFE);		// Switch bank2 VFE
			if((mstReadByte(BK2_03_STATUS3) & 0x80) != 0)		// if VCR mode detect
			{
				g_bVCRMode = 1;	//20050921 for VCR
				mstWriteByte(BK2_76_656_CTRL1, 0x02);		// Enable 656 mode
				mstWriteByte(GEN_00_REGBK, REGBANKSCALER);	// Switch bank0 Scaler
			
				//---------------20050921 for VCR------------------------------------
				//mstWriteByte(BK0_E8_HSTOL, 0x3F);		// Set HSync. tolerance to MAX.
				mstWriteByte(GEN_00_REGBK, REGBANKVCF);	// Switch bank3 comb filter
				mstWriteByte(BK3_10_COMBCFGA, 0x00);		// set 1D(Notch) mode
				mstWriteByte(GEN_00_REGBK, REGBANKSCALER);	// Switch bank0 Scaler
				//---------------20050921 for VCR------------------------------------
			}
			else
			{
				g_bVCRMode = 0;	//20050921 for VCR
				mstWriteByte(BK2_76_656_CTRL1, 0x00);		// disable 656 mode
				mstWriteByte(GEN_00_REGBK, REGBANKSCALER);	// Switch bank0 Scaler
				mstWriteByte(BK0_E8_HSTOL, 0x05);		// Set HSync. tolerance to default

				//---------------20050921 for VCR------------------------------------
				mstWriteByte(GEN_00_REGBK, REGBANKVCF);	// Switch bank3 comb filter
				mstWriteByte(BK3_10_COMBCFGA, 0x02);		// // set 2D comb filter mode
				mstWriteByte(GEN_00_REGBK, REGBANKSCALER);	// Switch bank0 Scaler
				//---------------20050921 for VCR------------------------------------
			}
		}
		else if(tOSDSourcSELSequence[Display.ucSourceSEL] == CCIR656)
	#else
		if ((tOSDSourcSELSequence[Display.ucSourceSEL] <= SVIDEO2))
		{
			mstWriteByte(GEN_00_REGBK, REGBANKVFE);		// Switch bank2 VFE
			if((mstReadByte(BK2_03_STATUS3) & 0x80) != 0)		// if VCR mode detect
			{
				g_bVCRMode = 1;	//20050921 for VCR
			}
			else
			{
				g_bVCRMode = 0;	//20050921 for VCR
			}

			mstWriteByte(GEN_00_REGBK, REGBANKSCALER);		// Switch bank0
			if((mstReadByte(BK0_EF_STATUS2) & _BIT2+_BIT3) == 0x04)		// if all odd field detect
			{
				g_bAllOddFiled = 1;	//20051031 for all odd field
			}
			else
			{
				g_bAllOddFiled = 0;	//200510311 for all odd field
			}
			
		}
		else if((tOSDSourcSELSequence[Display.ucSourceSEL] == CCIR656) && (g_ucSyncStableCounter == 0))
	#endif
		// 20050722 add by Antony for CCIR656 display abnormal
		
		{
			mstWriteByte(BK0_E2_SWRST0, 0x20);			// Reset Digital input port
			miscDelay1ms(20);
			mstWriteByte(BK0_E2_SWRST0, 0x00);
			miscDelay1ms(50);
		}
		mstWriteByte(BK0_18_INTSTA, 0x00);
		mstWriteByte(BK0_1E_INTSTD, 0x00);

		if(g_ucSyncStableCounter > SYNC_CHECK_TIMES)
		{
			g_ucSystemFlag |= NO_INPUT_SIGNAL_FLAG;
			g_ucSystemFlag &= ~INPUT_TIMING_CHANGE_FLAG;
			
			if ((Display.ucSystemStauts & POWER_STATUS_FLAG)!=0)
			{
				miscTurnOnPanel();
				SET_LED_ON();

				if ((g_ucSystemFlag & FIRST_AC_ON_FLAG) != FALSE)	//20050908 kevin
				{
					g_ucSystemFlag &= ~FIRST_AC_ON_FLAG;	
					osdOsdInitial();
					//osdOSDDrawSourceLable();
				}
			}
			else
			{
				mstPowerManagement(PM_POWER_OFF);
			}
		}
		else
			g_ucSyncStableCounter++;
	
		return;
		
	}
	else
	{
		g_ucSyncStatus = mstSyncDetect();
	
		if (((g_ucSyncStatus&SYNC_LOSS_MASK)!=0) && (g_ucSyncStableCounter < SYNC_CHECK_TIMES))
		{
			g_ucSyncStableCounter++;
			g_ucSystemFlag &= ~INPUT_SIGNAL_STABLE_FLAG;
			return;
		}
		else
		{
			if ((g_ucSyncStatus&SYNC_LOSS_MASK)!=0)
			{
				g_ucSystemFlag |= NO_INPUT_SIGNAL_FLAG;
			#if RS232DBG
				sysWriteString("No Signal Input !\x0d\x0a");
			#endif	//RS232DBG
			
			#if (MARIA_TYPE_SEL == MARIA_1)
				mstResetVedioDecoder();//20050905
			#endif
			}
			else
			{
				if((g_ucSystemFlag & INPUT_SIGNAL_STABLE_FLAG)==0)
				{
				#if(MARIA_TYPE_SEL == MARIA_1)
					mstWriteByte(GEN_00_REGBK, REGBANKVFE);//20050902
					mstWriteByte(BK2_43_AGC_CTRL1, 0x14);//20050902
					mstWriteByte(GEN_00_REGBK, REGBANKSCALER);//20050902
					mstSyncVDGainHandler(1);
				#endif
					g_ucSyncStableCounter = 0;
					g_ucSystemFlag |= INPUT_SIGNAL_STABLE_FLAG;
					return;	//20050908  kevin, Antony
				}
				else
				{
					if(g_ucSyncStableCounter < SYNC_STABLE_TIMES)
					{
						g_ucSyncStableCounter++;
						return;
					}
				}
			
			#if RS232DBG
				sysWriteString("Signal Input !\x0d\x0a");
				sysWriteString("BK3_72: ");
				sysWriteHex(g_ucVDStatus, 1);
				sysWriteString(tChangeLine);
				sysWriteString("Stable Counter: ");
				sysWriteDec(g_ucSyncStableCounter);
				sysWriteString(tChangeLine);
			#endif	//RS232DBG

			#if !DEMODULELATOR_MODE
				mstWriteByte(GEN_00_REGBK, REGBANKVCF); 	//Switch bank3 VCF
				// Set HSYNC Jitter Tolerance for H-position lock stable
				mstWriteByte(BK3_46_HSJITTLRN1, 0x00);	
				mstWriteByte(BK3_47_HSJITTLRN2, 0x00);	
				
				miscDelay1ms(25);
				// Restore HSYNC Jitter Tolerance default setting for enter 2D mode
				mstWriteByte(BK3_46_HSJITTLRN1, 0x08);	
				mstWriteByte(BK3_47_HSJITTLRN2, 0x20);	
				
				mstWriteByte(GEN_00_REGBK, REGBANKSCALER);		//Switch bank0 Scaler
			
			#endif	//DEMODULELATOR_MODE

			#if ENABLE_VD_COLOR_DETECT
				mstVDColorBurstHandler(VD_COLOR_BURST_HANDLER_RESET);
			#endif	// ENABLE_VD_COLOR_DETECT
			
				g_ucSystemFlag &= ~NO_INPUT_SIGNAL_FLAG;
			
				g_ucHTtuneCount = 0;		// 20050804 Antony
				g_ucHTtuneTimer = 20;		// 20050812 Antony
				g_uwHTtuneValue = 0;		// 20050804 Antony
				
				g_uwHcount = mstReadWord(BK0_EB_HSPRD_H) & 0x1FFF;	// Get H Period count
				g_uwVcount = mstReadWord(BK0_ED_VTOTAL_H) & 0x7FF;	// Get V period count

			#if RS232DBG
				sysWriteString("HSTOL: ");
				sysWriteUartHex4(g_uwHcount, 1);
				sysWriteString(tChangeLine);
				sysWriteString("VSTOL: ");
				sysWriteUartHex4(g_uwVcount, 1);
				sysWriteString(tChangeLine);
				sysWriteString(tChangeLine);
			#endif	//RS232DBG

				// 20050823 added by Antony for double check signal format
				if ((tOSDSourcSELSequence[Display.ucSourceSEL] <= SVIDEO2))
				{
				#if (PANEL_TYPE_SEL != PNL_PVI10_AT)//20050922 (the driving way is differennt)
					mstPatchFullOddField();
				#endif
				
				#if (MARIA_TYPE_SEL == MARIA_1)	
					mstWriteByte(GEN_00_REGBK, REGBANKVFE); 	// Switch bank2 VFE
					
					ucTemp = mstReadByte(BK2_01_STATUS1);		//20050930 Antony
					if((ucTemp & 0x07) == 0)
						g_bFSC443 = 1;
					else
						g_bFSC443 = 0;
					
					ucTemp = mstReadByte(BK2_02_STATUS2);
					if((ucTemp & 0x03) == 0x02 && (ucTemp & 0x30) == 0x20)
						g_ucSyncStatus |=  PAL_MODE_B;
					else
						g_ucSyncStatus &=  ~PAL_MODE_B;

					if ((g_uwVcount > 575) && ((g_ucSyncStatus & PAL_MODE_B) == 0))	//20050902 kevin
					{
						g_ucSyncStableCounter = 0;
						return;
					}
				#endif
				
				}			
			
			
				// For MARIA 2 20050930 Antony
				#if 0 //(MARIA_TYPE_SEL == MARIA_2)
				mstVDSetupMode(g_bFSC443);
				#endif
				
				// Do change mode routine
				if (tOSDSourcSELSequence[Display.ucSourceSEL] <= CVBS2) 
				{
				#if (MARIA_TYPE_SEL == MARIA_2)
					mstSyncCVBSModeSet(g_ucVDStatus);
				#else