sync.c

MST720-DEMO程序

	g_ucSystemFlag &= ~INPUT_SIGNAL_STABLE_FLAG;
	mstSetBrightness(Display.ucBrightness);

	if((g_ucSystemFlag & FIRST_AC_ON_FLAG) != FIRST_AC_ON_FLAG)	//20050908 kevin
		miscDelay1ms(200);
}

void mstSyncCVBSModeSet(BYTE ucSyncStatus)
{
#if (MARIA_TYPE_SEL == MARIA_2)
	if(ucSyncStatus & _BIT7)
	{
		mstWriteDataTable(tSyncCVBSNTSCTable);
		// PATCH setting add follow next:
		mstWriteByte(GEN_00_REGBK, REGBANKVCF); // Switch to Bank3 VCF
		mstWriteByte(BK3_48_BSTLVL_TH, 0x00);
	/*#if (PANEL_WIDTH > 900)
		mstWriteByte(GEN_00_REGBK, REGBANKVFE); // Switch to Bank2 VFE
		mstWriteByte(BK2_7B_656_HDEW, 0xE0);
	#elif (PANEL_WIDTH > 720)
		mstWriteByte(GEN_00_REGBK, REGBANKVFE);	// Switch to Bank2 VFE
		mstWriteByte(BK2_7B_656_HDEW, 0xE0);
	#endif*/
		mstWriteByte(GEN_00_REGBK, REGBANKSCALER);	// Switch to Bank0 Scaler
	}
	else if(ucSyncStatus & _BIT6)
	{
		mstWriteDataTable(tSyncCVBSPALTable);
		// PATCH setting add follow next:
		mstWriteByte(GEN_00_REGBK, REGBANKVCF); // Switch to Bank3 VCF
		mstWriteByte(BK3_48_BSTLVL_TH, 0x00);
	/*#if (PANEL_WIDTH > 900)
		mstWriteByte(GEN_00_REGBK, REGBANKVFE); // Switch to Bank2 VFE
		mstWriteByte(BK2_7B_656_HDEW, 0xF5);
	#elif (PANEL_WIDTH > 720)
		mstWriteByte(GEN_00_REGBK, REGBANKVFE); // Switch to Bank2 VFE
		mstWriteByte(BK2_7B_656_HDEW, 0xF5);
	#endif*/
		mstWriteByte(GEN_00_REGBK, REGBANKSCALER);	// Switch to Bank0 Scaler
	}

#else

#if !DEMODULELATOR_MODE
	if((ucSyncStatus & DEMODULATION_MODE1_B) != 0)
		mstSyncDemodulationModeSet(1);		// Set demodulation to mode 1
	else
		mstSyncDemodulationModeSet(0);		// Set demodulation to mode 0
#endif	// !DEMODULELATOR_MODE

	if ((ucSyncStatus & PAL_MODE_B) != 0)
	{
		mstWriteDataTable(tSyncCVBSPALTable);
		// PATCH setting add follow next:
		mstWriteByte(GEN_00_REGBK, REGBANKVFE);	// Switch to Bank2 VFE
		mstWriteByte(BK2_4D_BRST_WINDOW2, 0xA9);
		mstWriteByte(BK2_69_SRC_CTRL1, 0x82);
		mstWriteByte(GEN_00_REGBK, REGBANKSCALER);	// Switch to Bank0 Scaler
		//20050921 mask for VCR //mstWriteByte(BK0_E5_MDCTRL, 0x05);		// 20050812 Antony
	}
	else
	{
		
		mstWriteDataTable(tSyncCVBSNTSCTable);	// Load NTSC timing table

#if !DEMODULELATOR_MODE
		if((ucSyncStatus & DEMODULATION_MODE1_B) != 0)
		{
			mstWriteDataTable(tSyncCVBSNTSC443Table);	// Load NTSC443 timing table
			// PATCH setting add follow next:
		}
#endif	// !DEMODULELATOR_MODE

		// PATCH setting add follow next:
		mstWriteByte(GEN_00_REGBK, REGBANKVFE);	// Switch to Bank2 VFE
		mstWriteByte(BK2_4D_BRST_WINDOW2, 0xA0);
		mstWriteByte(BK2_69_SRC_CTRL1, 0x82);
		mstWriteByte(GEN_00_REGBK, REGBANKSCALER);	// Switch to Bank0 Scaler
		//20050921 mask for VCR//mstWriteByte(BK0_E5_MDCTRL, 0x04);		// 20050812 Antony
	}
	
	mstWriteByte(BK0_36_VDSUSG, (mstReadByte(BK0_36_VDSUSG) | 0x0C));	// 20050812 Antony
#endif
}

void mstSyncSVideoModeSet(BYTE ucSyncStatus)
{
#if (MARIA_TYPE_SEL == MARIA_2)
	if(ucSyncStatus & _BIT7)
	{
		mstWriteDataTable(tSyncSVideoNTSCTable);
		// PATCH setting add follow next:
		mstWriteByte(GEN_00_REGBK, REGBANKVCF); // Switch to Bank3 VCF
		if((ucSyncStatus & 0x07) == 0x02)				// For PAL-M mode
			mstWriteByte(BK3_48_BSTLVL_TH, 0x00);
		else
			mstWriteByte(BK3_48_BSTLVL_TH, 0x20);

	/*#if (PANEL_WIDTH > 900)
		mstWriteByte(GEN_00_REGBK, REGBANKVFE); // Switch to Bank2 VFE
		mstWriteByte(BK2_7B_656_HDEW, 0xE0);
	#elif (PANEL_WIDTH > 720)
		mstWriteByte(GEN_00_REGBK, REGBANKVFE); // Switch to Bank2 VFE
		mstWriteByte(BK2_7B_656_HDEW, 0xE0);
	#endif*/
		mstWriteByte(GEN_00_REGBK, REGBANKSCALER);	// Switch to Bank0 Scaler
	}
	else if(ucSyncStatus & _BIT6)
	{
		mstWriteDataTable(tSyncSVideoPALTable);
		// PATCH setting add follow next:
		mstWriteByte(GEN_00_REGBK, REGBANKVCF); // Switch to Bank3 VCF
		mstWriteByte(BK3_48_BSTLVL_TH, 0x00);
		
	/*#if (PANEL_WIDTH > 900)
		mstWriteByte(GEN_00_REGBK, REGBANKVFE); // Switch to Bank2 VFE
		mstWriteByte(BK2_7B_656_HDEW, 0xF5);
	#elif (PANEL_WIDTH > 720)
		mstWriteByte(GEN_00_REGBK, REGBANKVFE); // Switch to Bank2 VFE
		mstWriteByte(BK2_7B_656_HDEW, 0xF5);
	#endif*/
		mstWriteByte(GEN_00_REGBK, REGBANKSCALER);	// Switch to Bank0 Scaler
		}
	
#else

#if !DEMODULELATOR_MODE
	if((ucSyncStatus & DEMODULATION_MODE1_B) != 0)
		mstSyncDemodulationModeSet(1);		// Set demodulation to mode 1
	else
		mstSyncDemodulationModeSet(0);		// Set demodulation to mode 0
#endif	// !DEMODULELATOR_MODE

	if ((ucSyncStatus & PAL_MODE_B) != 0)
	{
		
		mstWriteDataTable(tSyncSVideoPALTable);
		// PATCH setting add follow next:
		mstWriteByte(GEN_00_REGBK, REGBANKVFE);	//Switch to Bank2 VFE
		mstWriteByte(BK2_4D_BRST_WINDOW2, 0xA9);
		mstWriteByte(BK2_69_SRC_CTRL1, 0x83);
	#if (DEMODULELATOR_MODE)
		mstWriteByte(BK2_2D_VDFD_CTRL3, mstReadByte(BK2_2D_VDFD_CTRL3)|0x02);		// For mode 1 Chroma Delay issue
	#endif	// DEMODULELATOR_MODE
		mstWriteByte(GEN_00_REGBK, REGBANKSCALER);	//Switch to Bank0 Scaler
		//20050921 mask for VCR//mstWriteByte(BK0_E5_MDCTRL, 0x05);		// 20050812 Antony
	}
	else
	{
		mstWriteDataTable(tSyncSVideoNTSCTable);
		
#if !DEMODULELATOR_MODE
		if((ucSyncStatus & DEMODULATION_MODE1_B) != 0)
		{
			mstWriteDataTable(tSyncSVideoNTSC443Table);	// Load NTSC443 timing table
			// PATCH setting add follow next:
			mstWriteByte(GEN_00_REGBK, REGBANKVFE);		//Switch to Bank2 VFE
			mstWriteByte(BK2_4D_BRST_WINDOW2, 0xA0);
			mstWriteByte(GEN_00_REGBK, REGBANKSCALER);		//Switch to Bank0 Scaler
			return;
		}
#endif	// !DEMODULELATOR_MODE

		// PATCH setting add follow next:
		mstWriteByte(GEN_00_REGBK, REGBANKVFE);	//Switch to Bank2 VFE
		mstWriteByte(BK2_4D_BRST_WINDOW2, 0xA0);
		if ((mstReadByte(BK2_01_STATUS1) & 0x07) == 0x00)
		mstWriteByte(BK2_69_SRC_CTRL1, 0x85);
		else
		mstWriteByte(BK2_69_SRC_CTRL1, 0x87);
	#if (DEMODULELATOR_MODE)
		mstWriteByte(BK2_2D_VDFD_CTRL3, mstReadByte(BK2_2D_VDFD_CTRL3)|0x02);		// For mode 1 Chroma Delay issue
	#endif	// DEMODULELATOR_MODE
		mstWriteByte(GEN_00_REGBK, REGBANKSCALER);	//Switch to Bank0 Scaler
		//20050921 mask for VCR//mstWriteByte(BK0_E5_MDCTRL, 0x04);		// 20050812 Antony
	}
	mstWriteByte(BK0_36_VDSUSG, (mstReadByte(BK0_36_VDSUSG) | 0x0C));	// 20050812 Antony

#endif
}

void mstSyncVGAModeSet(BYTE ucSyncStatus)
{
	BYTE ucTemp;
	
	mstWriteDataTable(tSyncVGAModeTable);
	ucSyncStatus ^= (VSYNC_NEGATIVE_B+HSYNC_NEGATIVE_B);

	ucTemp = mstReadByte(BK0_03_IPCTRL2);
	ucTemp &= 0xE7;					// Clear BK0.03h[4:3]
	ucTemp |= (ucSyncStatus << 3);			// Set BK0.03h[4:3] by input sync polarity
	mstWriteByte(BK0_03_IPCTRL2, ucTemp);
	

}


void mstSyncYPbPrModeSet(BYTE ucSyncStatus)
{
	WORD uwVcount;
	
	if((ucSyncStatus & INTERLANCE_MODE_B) == 0)
	{
		uwVcount = mstReadWord(BK0_ED_VTOTAL_H) & 0x7FF;
		
		if (uwVcount > 560)
			mstWriteDataTable(tSyncYPbPrPALTable);
		else
			mstWriteDataTable(tSyncYPbPrNTSCTable);

	}
	else
	{
		if ((ucSyncStatus & PAL_MODE_B) != 0)
			mstWriteDataTable(tSyncYCbCrPALTable);
		else
			mstWriteDataTable(tSyncYCbCrNTSCTable);
	}
}

void mstSyncCCIRModeSet(BYTE ucSyncStatus)
{
	if ((ucSyncStatus & PAL_MODE_B) != 0)
		mstWriteDataTable(tSyncCCIRPALTable);
	else
		mstWriteDataTable(tSyncCCIRNTSCTable);
}

void mstSyncCheckSignal(void)
{
#if ((MARIA_TYPE_SEL == MARIA_2) && ENABLE_NEW_SYNC)
	BYTE ucBank;
	BYTE ucTemp_VDStatus;
	BYTE ucTemp0_1E = 0;

	ucBank = mstReadByte(GEN_00_REGBK);

	if(tOSDSourcSELSequence[Display.ucSourceSEL] < VGA)
	{
		mstWriteByte(GEN_00_REGBK, REGBANKVCF);

		ucTemp_VDStatus = mstReadByte(BK3_72_COMB_STSC);

		if((ucTemp_VDStatus != g_ucVDStatus) && ((g_ucSystemFlag&INPUT_TIMING_CHANGE_FLAG) == 0))
		{
			mstEnableMute();
			g_ucVDStatus = ucTemp_VDStatus;
			g_ucSystemFlag |= INPUT_TIMING_CHANGE_FLAG;
			g_ucSystemFlag &= ~INPUT_SIGNAL_STABLE_FLAG;
			g_ucSyncStableCounter = 0;
			
		#if (MARIA_TYPE_SEL == MARIA_2)
			mstResetVedioDecoder();
		#endif
		
		#if RS232DBG
			sysWriteString("VD Status change !\x0d\x0a");
			sysWriteString("BK3_72:	");
			sysWriteHex(ucTemp_VDStatus, 1);
			sysWriteString(tChangeLine);
		#endif	//RS232DBG
		}
	}
	else
	{
		mstWriteByte(GEN_00_REGBK, REGBANKSCALER);

		ucTemp0_1E = mstReadByte(BK0_1E_INTSTD);
		if(((ucTemp0_1E & 0x1F)!=0) && ((g_ucSystemFlag&INPUT_TIMING_CHANGE_FLAG) == 0))
		{
			mstEnableMute();
			g_ucSystemFlag |= INPUT_TIMING_CHANGE_FLAG;
			g_ucSystemFlag &= ~INPUT_SIGNAL_STABLE_FLAG;
			g_ucSyncStableCounter = 0;

		#if RS232DBG
			sysWriteString("Sync change flag set \x0d\x0a ");
			sysWriteString("BK0_1E_INTSTD:	");
			sysWriteHex(ucTemp0_1E, 1);
			sysWriteString(tChangeLine);
		#endif	//RS232DBG
		}
	}

	mstWriteByte(GEN_00_REGBK, ucBank);

#else
	BYTE ucTemp0_18 = 0;
	BYTE ucTemp0_1E = 0;
	BYTE ucTemp3_72 = 0;
	
	ucTemp0_1E = mstReadByte(BK0_1E_INTSTD);
	ucTemp0_18 = mstReadByte(BK0_18_INTSTA);
	
	if(((ucTemp0_1E & 0x1F)!=0) && ((g_ucSystemFlag&INPUT_TIMING_CHANGE_FLAG) == 0))
	{
		if(g_bVCRMode && (ucTemp0_1E & 0x1C))	//20050921 for VCR
			return;
		
		mstEnableMute();

#if (MARIA_TYPE_SEL == MARIA_2)
		mstWriteByte(GEN_00_REGBK, REGBANKVCF);
		ucTemp3_72 = mstReadByte(BK3_72_COMB_STSC);
		mstWriteByte(GEN_00_REGBK, REGBANKSCALER);
		if((g_ucSystemFlag & NO_INPUT_SIGNAL_FLAG) && (ucTemp3_72 & _BIT3))
		{
			return;
		}
#endif
		g_ucSystemFlag |= INPUT_TIMING_CHANGE_FLAG;
		g_ucSystemFlag &= ~INPUT_SIGNAL_STABLE_FLAG;
		g_ucSyncStableCounter = 0;
#if 0 //(MARIA_TYPE_SEL == MARIA_2)
		mstResetVedioDecoder();
#endif

	#if RS232DBG
		sysWriteString("Sync change flag set \x0d\x0a ");
		sysWriteString("BK0_1E_INTSTD:	");
		sysWriteHex(ucTemp0_1E, 1);
		sysWriteString(tChangeLine);
	#endif	//RS232DBG
	}
	//else if((( ucTemp0_18 & 0xCD) != 0) && ((g_ucSystemFlag&INPUT_TIMING_CHANGE_FLAG) == 0))
	else if((( ucTemp0_18 & 0xCC) != 0) && ((g_ucSystemFlag&INPUT_TIMING_CHANGE_FLAG) == 0))//20050905
	{
		if((g_ucSystemFlag & NO_INPUT_SIGNAL_FLAG) == 0)	// have signal input
		{
			mstEnableMute();
			g_ucSystemFlag |= INPUT_TIMING_CHANGE_FLAG;
			g_ucSystemFlag &= ~INPUT_SIGNAL_STABLE_FLAG;
			g_ucSyncStableCounter = 0;

	#if RS232DBG
			sysWriteString("Sync change flag set \x0d\x0a ");
			sysWriteString("BK0_18_INTSTA_L:  ");
			sysWriteHex(ucTemp0_18, 1);
			sysWriteString(tChangeLine);
	#endif	//RS232DBG
		}
		else						// no signal input
		{
			if((ucTemp0_18 & 0xC0)!=0)
			{
				g_ucSystemFlag |= INPUT_TIMING_CHANGE_FLAG;
				g_ucSystemFlag &= ~INPUT_SIGNAL_STABLE_FLAG;
				g_ucSyncStableCounter = 0;
				
		#if RS232DBG
				sysWriteString("Sync change flag set \x0d\x0a ");
				sysWriteString("BK0_18_INTSTA_H:  ");
				sysWriteHex(ucTemp0_18, 1);
				sysWriteString(tChangeLine);
		#endif	//RS232DBG
			}
		}
		
	}

	if( (g_ucSystemFlag & INPUT_TIMING_CHANGE_FLAG) != 0)
		return;
	
	// 20050823 Antony for (check sync. status for full odd field)
	if((g_ucSyncStatus & INTERLANCE_MODE_B) != (mstReadByte(BK0_EF_STATUS2) & INTERLANCE_MODE_B))
	{
		mstEnableMute();
		g_ucSystemFlag |= INPUT_TIMING_CHANGE_FLAG;
		g_ucSystemFlag &= ~INPUT_SIGNAL_STABLE_FLAG;
		g_ucSyncStableCounter = 0;
	}

#endif
}

BYTE mstSyncDetect(void)
{
	WORD uwHFreq, uwVFreq, uwFreqTemp;
	BYTE ucSyncStatus, ucSyncTemp;
#if ((MARIA_TYPE_SEL == MARIA_2) && ENABLE_NEW_SYNC)
	BYTE ucBank;
	BYTE ucTempBK3_72;
#endif

	ucSyncStatus = 0;

#if ((MARIA_TYPE_SEL == MARIA_2) && ENABLE_NEW_SYNC)
	ucBank = mstReadByte(GEN_00_REGBK);

	if(tOSDSourcSELSequence[Display.ucSourceSEL] < VGA)
	{
		mstWriteByte(GEN_00_REGBK, REGBANKVCF);		// Switch bank3 VCF
		ucTempBK3_72 = mstReadByte(BK3_72_COMB_STSC);
		if((ucTempBK3_72 & _BIT3) != 0)
		{
			ucSyncStatus |= SYNC_LOSS_MASK;