📄 pnl_au20_d.h

📁 MST720-DEMO程序
💻 H
📖 第 1 页 / 共 2 页
字号:
上一页 12
	0x92, 0x05,
	0x00,

	7, BK0_30_SRH_L,			// Set H&V scaling rate
	0x00, 0x40, 0xC9,
	0xAD, 0x50, 0x86, 
	0x0C,
	
#else

	9, BK0_05_SPRVST_L,		// Set Capture
	0x28,0x00,
	0xEE,0x00,
	0xD4, 0x01,
	0xD8, 0x05,
	0x00,

	7, BK0_30_SRH_L,			// Set H&V scaling rate
	0x00, 0xF0, 0xC8,
	0x00, 0x36, 0x86, 
	0x0C,
	
#endif

	// 1, BK0_E5_MDCTRL,//20050921 mask for VCR
	// 0x04,
	-1
};

BYTE code tSyncSVideoPALTable[] = 
{

	1, GEN_00_REGBK,			// select register bank scaler
	REGBANKSCALER,

	//20050921 (set bit3 to avoid BK0_1D produce wrong message for VCR) 
	1, BK0_03_IPCTRL2,		// Set Capture  
	0x88,					// BK0_03_IPCTRL2,

#if DEMODULELATOR_MODE

	9, BK0_05_SPRVST_L,
	0x30, 0x00, 
	0x5f, 0x00,
	0x34, 0x02,
	0x82, 0x05,
	0x00,

	7, BK0_30_SRH_L,			// Set H&V scaling rate
	0x00, 0x60, 0xC9,
	0x00, 0x82, 0x87,
	0x0C,
	
#else

	9, BK0_05_SPRVST_L,
	0x2C, 0x00, 
	0x5A, 0x01,
	0x34, 0x02,
	0x38, 0x07,
	0x00,

	7, BK0_30_SRH_L,			// Set H&V scaling rate
	0x00, 0x20, 0xC7,
	0x00, 0x82, 0x87, 
	0x0C,
	
#endif
	// 1, BK0_E5_MDCTRL,//20050921 mask for VCR
	// 0x05,

	-1
};

/******************************* VGA Timing Table ****************************/
BYTE code tSyncVGAModeTable[] =
{
	1, GEN_00_REGBK,			// select register bank scaler
	REGBANKSCALER,

	11, BK0_03_IPCTRL2,		// Set Capture
	0x98, 0x03,
	0x24, 0x00, 
	0x88, 0x00,
	0xD4, 0x01,
	0x3A, 0x05,
	0x00,

	3, BK0_0F_ASCTRL,		// 
	0x10, 0x00, 0x00,

	7, BK0_30_SRH_L,			// Set H&V scaling rate
	0x00, 0x00, 0xCA,
	0x00, 0x70, 0xCC, 
	0x00,

	1, GEN_00_REGBK,			// select register bank ADC
	REGBANKADC,
	
	2, BK1_02_PLLDIVM,		// ADC sample clock setting
	0x63, 0xD0,

	2, BK1_10_CLKCTRL1,		// ADC phase setting
	0x08, 0x04,

	1, GEN_00_REGBK,			// select register bank scaler
	REGBANKSCALER,

	-1
};

/************************** Component Timing Table ***************************/
/***** Interlace input *****/
BYTE code tSyncYCbCrNTSCTable[] = 
{
	1, GEN_00_REGBK,			// select register bank ADC
	REGBANKADC,			// 00h
	
	2, BK1_02_PLLDIVM,		// ADC sample clock setting
	0x6B, 0x10,			// BK1.02h, BK1.03h

	3, BK1_07_ROFFS_ADC,//kevin for return from 1080i
	0x80, 0x60, 0x80,
	1, GEN_00_REGBK,			// select register bank scaler
	REGBANKSCALER,

	9, BK0_05_SPRVST_L,		// Set Capture
	0x30, 0x00, 
	0x94, 0x00,
	0xD4, 0x01,
	0x7D, 0x05,
	0x00,

	1, BK0_0F_ASCTRL,		// Line buffer
	0x20,				// BK0.0Fh

	7, BK0_30_SRH_L,			// Set H&V scaling rate
	0x00, 0x40, 0xC9,
	0x00, 0x3A, 0x86, 
	0x0C,

	-1,

};

BYTE code tSyncYcbCr1080iTable[] = //kevin
{
	1, GEN_00_REGBK,			// select register bank ADC
	REGBANKADC,			// 00h
	
	2, BK1_02_PLLDIVM,		// ADC sample clock setting
	0x68, 0xD0,			// BK1.02h, BK1.03h

	3, BK1_07_ROFFS_ADC,
	0x80, 0x00, 0x80,

	1, BK1_85_M_BRI,
	0x18,

	1, GEN_00_REGBK,			// select register bank scaler
	REGBANKSCALER,

	9, BK0_05_SPRVST_L,		// Set Capture
	0x6B, 0x00, 
	0xAF, 0x00,
	0x00, 0x04,
	0x74, 0x05,
	0x00,

	1, BK0_0F_ASCTRL,		// Line buffer
	0x20,				// BK0.0Fh

	7, BK0_30_SRH_L,			// Set H&V scaling rate
	0x00, 0x70, 0xC9,
	0x99, 0xa9, 0x8d, 
	0x0C,

	-1,

};

BYTE code tSyncYCbCrPALTable[] = 
{
	1, GEN_00_REGBK,			// select register bank ADC
	REGBANKADC,			// 00h
	
	2, BK1_02_PLLDIVM,		// ADC sample clock setting
	0x6B, 0xD0,			// BK1.02h, BK1.03h
	3, BK1_07_ROFFS_ADC,//kevin for return from 1080i
	0x80, 0x60, 0x80,

	1, GEN_00_REGBK,			// select register bank scaler
	REGBANKSCALER,

	9, BK0_05_SPRVST_L,		// Set Capture
	0x34, 0x00, 
	0xAF, 0x00,
	0x34, 0x02,
	0x74, 0x05,
	0x00,

	1, BK0_0F_ASCTRL,		// Line buffer
	0x20,				// BK0.0Fh

	7, BK0_30_SRH_L,			// Set H&V scaling rate
	0x00, 0x50, 0xC9,
	0x00, 0x82, 0x87, 
	0x0C,

	-1,

};

/***** Non-Interlace input *****/
BYTE code tSyncYPbPrNTSCTable[] = 
{
	1, GEN_00_REGBK,			// select register bank ADC
	REGBANKADC,			// 00h
	
	2, BK1_02_PLLDIVM,		// ADC sample clock setting
	0x6B, 0x10,			// BK1.02h, BK1.03h

	3, BK1_07_ROFFS_ADC,//kevin for return from 1080i
	0x80, 0x60, 0x80,
	1, GEN_00_REGBK,			// select register bank scaler
	REGBANKSCALER,

	9, BK0_05_SPRVST_L,		// Set Capture
	0x25, 0x00, 
	0x8E, 0x00,
	0xDB, 0x01,
	0x74, 0x05,
	0x00,

	1, BK0_0F_ASCTRL,		// Line buffer
	0x20,				// BK0.0Fh

	7, BK0_30_SRH_L,			// Set H&V scaling rate
	0x00, 0x40, 0xC9,
	0x00, 0xA8, 0x8C, 
	0x0C,

	-1,

};

BYTE code tSyncYPbPrPALTable[] = 
{
	1, GEN_00_REGBK,			// select register bank ADC
	REGBANKADC,			// 00h
	
	2, BK1_02_PLLDIVM,		// ADC sample clock setting
	0x6B, 0xD0,			// BK1.02h, BK1.03h
	3, BK1_07_ROFFS_ADC,//kevin for return from 1080i
	0x80, 0x60, 0x80,
	
	1, GEN_00_REGBK,			// select register bank scaler
	REGBANKSCALER,

	9, BK0_05_SPRVST_L,		// Set Capture
	0x28, 0x00, 
	0xA4, 0x00,
	0x34, 0x02,
	0x74, 0x05,
	0x00,

	1, BK0_0F_ASCTRL,		// Line buffer
	0x20,				// BK0.0Fh

	7, BK0_30_SRH_L,			// Set H&V scaling rate
	0x00, 0x60, 0xC9,
	0x00, 0x08, 0x8F, 
	0x0C,

	-1,

};

/**************************** CCIR656 Timing Table ***************************/
BYTE code tSyncCCIRNTSCTable[] =
{
	1, GEN_00_REGBK,			// select register bank scaler
	REGBANKSCALER,

	9, BK0_05_SPRVST_L,		// Set Capture
	0x20, 0x00,
	0x08, 0x00,
	0x34, 0x02,
	0xA0, 0x05, 
	0x00,

	7, BK0_30_SRH_L,			// Set H&V scaling rate
	0x00, 0x80, 0xC5,
	0x00, 0x00, 0x90, 0x1C,
	
	-1,


};


BYTE code tSyncCCIRPALTable[] = 
{
	1, GEN_00_REGBK,			// select register bank scaler
	REGBANKSCALER,

	9, BK0_05_SPRVST_L,		// Set Capture
	0x16, 0x00,
	0x08, 0x00,
	0x34, 0x02,
	0xA0, 0x05, 
	0x00,

	7, BK0_30_SRH_L,			// Set H&V scaling rate
	0x00, 0x80, 0xC5,
	0x00, 0xD0, 0x93, 0x10,

	-1,

};

///////////////////////////////////////////////////////
// TCON setting 
///////////////////////////////////////////////////////

// PTC Mode setting
#define SET_PTC_MODE1		0x8C	// PTC_MODE1(0xD0)
#define SET_PTC_MODE2		0x1E	// PTC_MODE2(0xD1)
#define SET_PTC_MODE3		0x82	// PTC_MODE3(0xD2)

// PTC Timming Setting
#define SET_FRP_TRAN		0x02	// GPO_FRP_TRAN(0xDC)
#define SET_STH_START		0x6F	// GPO_STH_START(0xDD)
#define SET_STH_WIDTH		0x03	// GPO_STH_WIDTH(0xDE)
#define SET_OEH_START		0x25	// GPO_OEH_START(0xDF)
#define SET_OEH_WIDTH		0x07	// GPO_OEH_WIDTH(0xE0)
#define SET_OEV_START		0x11	// GPO_OEV_START(0xE1)
#define SET_OEV_WIDTH		0x2D	// GPO_OEV_WIDTH(0xE2)
#define SET_CKV_START		0x01	// GPO_CKV_START(0xE3)
#define SET_CKV_START2		0x04	// GPO_CKV_START2(0xE4)
#define SET_CKV_WIDTH		0x5F	// GPO_CKV_WIDTH(0xE5)
#define SET_STV_LINE_TH 	0x45	// GPO_STV_LINE_TH(0xE6)
#define SET_STV_START		0x18	// GPO_STV_START(0xE7)
#define SET_STV_WIDTH		0x01	// GPO_STV_WIDTH(0xE8)
#define SET_OEV2_START		0x00	// GPO_OEV2_START(0xE9)
#define SET_OEV3_START		0x00	// GPO_OEV3_START(0xEA)
#define SET_H_ST_DLY_L		0x00	// H_ST_DLY_L(0xEB)
#define SET_H_ST_DLY_H		0x00	// H_ST_DLY_H(0xEC)
#define SET_CLK_DLY_SYNC_OUT	0x00	// CLK_DLY_SYNC_OUT(0xED)
#define SET_CKV_END2		0x00	// GPO_CKV_END2(0xEE)

#define SET_OEV2_WIDTH		0x54	// GPO_OEV2_WIDTH(0xCD)
#define SET_OEV3_WIDTH		0x54	// GPO_OEV3_WIDTH(0xCE)
#define SET_OEV_DELTA		0x54	// GPO_OEV_DELTA(0xCF)

// VCOM setting
#define SET_BVOM_DC		0xEF	//DEF_VCOM_DC	// BVOM_DC(0x43)
#define SET_BVOM_OUT		0xFF	//DEF_VCOM_AC	// BVOM_OUT(0x44)

// DAC setting
#define SET_VDAC_ADJ1		0x00	// VADC_ADJ1(0xAA)
#define SET_VDAC_ADJ2		0x00	// VDAC_ADJ2(0xAB)

#endif	// _SYNC_C_

///////////////////////////////////////////////////////
// TCON setting
///////////////////////////////////////////////////////

// VCOM setting
#define SET_BVOM_DC		0xEF	//DEF_VCOM_DC	// BVOM_DC(0x43)
#define SET_BVOM_OUT		0xFF	//DEF_VCOM_AC	// BVOM_OUT(0x44)

// DAC setting
#define SET_VDAC_ADJ1		0x00	// VADC_ADJ1(0xAA)
#define SET_VDAC_ADJ2		0x00	// VDAC_ADJ2(0xAB)

// Backlight PWM setting
#define SET_BACKLIGHT_PWM	0xFF	// for Bk1.F4h initial setting

#endif
上一页 12
💿 文件大小 1373 K
👤 上传用户 foreverxiluzai
📂 所属分类单片机开发
🏷️ 相关标签

#DEMO #MST #720 #程序
⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -