pnl_au25_at.h

MST720-DEMO程序

/******************************************************************************
 Copyright (c) 2003 MStar Semiconductor, Inc.
 All rights reserved.

 [Module Name]: Pnl_AU25_AT.h
 [Date]:        11-AUG-2005
 [Comment]:
   Panel parameters.[AU025CN00] 480X234
 [Reversion History]:
*******************************************************************************/

#ifndef __AU25_H
#define __AU25_H

///////////////////////////////////////////////
// Common setting
///////////////////////////////////////////////
#define PANEL_NAME		"AU25_AT"
#define PANEL_DOT_WIDTH 	102.5		// unit: um
#define PANEL_DOT_HEIGHT	163		// unit: um

//////////////////////////////////////////////
// Panel output
//////////////////////////////////////////////
#define PANEL_DITHER          	1		// 8/6 bits panel

#define PANEL_LVDS			0
#define PANEL_TTL             	0
#define PANEL_TCON            	0
#define PANEL_ANALOG_TCON	1

#define PANEL_SWAP_LVDS_POL 0
#define PANEL_SWAP_LVDS_CH	0
#define PANEL_LVDS_TI_MODE		0

#define PANEL_6BIT_OUT		0		// 0/1: 8BIT/6BIT out
#define PANEL_DITHER_ENABLE	1		// 0/1:Enable/Disable
#define PANEL_DITHER_CONTROL	0x0C+(PANEL_6BIT_OUT<<1)+PANEL_DITHER_ENABLE

#define PANEL_SWAP_8BIT_ML	0
#define PANEL_SWAP_6BIT_ML	0
#define PANEL_SWAP_RB		1
#define PANEL_SWAP_CONTROL	(PANEL_SWAP_RB<<2)+(PANEL_SWAP_6BIT_ML<<1)+PANEL_SWAP_8BIT_ML

#define PANEL_DCLK_DELAY	0x0		// Range (0~F)
#define PANEL_INV_DCLK        	1		// 1: Invert output DCLK
#define PANEL_INV_DE          	0		// 1: Invert output DE
#define PANEL_INV_VSYNC       	0		// 1: Invert output VSYNC
#define PANEL_INV_HSYNC       	0		// 1: Invert output HSYNC
#define PANEL_SYNC_CONTROL	(PANEL_DCLK_DELAY<<4)+(PANEL_INV_DCLK<<3)+(PANEL_INV_DE<<2) \
				+(PANEL_INV_VSYNC<<1)+PANEL_INV_HSYNC	
// Lock Y line
#define PANEL_LOCK_Y_LINE	0

///////////////////////////////////////////////
// Output tmming setting
///////////////////////////////////////////////
// driving current setting (0x00=4mA, 0x01=6mA, 0x02=8mA, 0x03=12mA)
#define PANEL_DCLK_CURRENT	0x01		// DCLK current
#define PANEL_DE_CURRENT	0x01		// DE signal current
#define PANEL_HS_CURRENT	0x01		// HSYNC current
#define PANEL_VS_CURRENT	0x01		// VSYNC current
#define PANEL_BM_CURRENT	0x01		// B data High-Nibble current
#define PANEL_BL_CURRENT	0x01		// B data Low-Nibble current
#define PANEL_GM_CURRENT	0x01		// G data High-Nibble current
#define PANEL_GL_CURRENT	0x01		// G data Low-Nibble current
#define PANEL_RM_CURRENT	0x01		// R data High-Nibble current
#define PANEL_RL_CURRENT	0x01		// R data Low-Nibble current

#define PANEL_ADCLK_CURRENT	0x01		// Analog Panel DCLK current

#define PANEL_ON_TIMING1	30		// time between panel & data while turn on power
#define PANEL_ON_TIMING2	100		// time between data & back light while turn on power
#define PANEL_OFF_TIMING1	20		// time between back light & data while turn off power
#define PANEL_OFF_TIMING2	20		// time between data & panel while turn off power

#define PANEL_HSYNC_WIDTH		20
#define PANEL_HSYNC_BACK_PORCH	65

#define PANEL_VSYNC_WIDTH		12
#define PANEL_VSYNC_BACK_PORCH	24

#define PANEL_HSTART		(PANEL_HSYNC_WIDTH + PANEL_HSYNC_BACK_PORCH)
#define PANEL_VSTART		0		//(PANEL_VSYNC_WIDTH + PANEL_VSYNC_BACK_PORCH)
#define PANEL_WIDTH		480
#define PANEL_HEIGHT		234
#define PANEL_HTOTAL		600
#define PANEL_VTOTAL		262

#define PANEL_MAX_HTOTAL	660
#define PANEL_MIN_HTOTAL	540
#define PANEL_MAX_VTOTAL	268
#define PANEL_MIN_VTOTAL	256
#define PANEL_DCLK		(((DWORD)PANEL_HTOTAL*PANEL_VTOTAL*60)/1000000)
#define PANEL_MAX_DCLK		49
#define PANEL_MIN_DCLK		39

///////////////////////////////////////////////
// Panel color default setting
///////////////////////////////////////////////
#define _COLOR_DEF_CONTRAST		0x88
#define _COLOR_DEF_SATURATION		0x88
#define _COLOR_DEF_HUE			50
#define _COLOR_DEF_CB			0x96
#define _COLOR_DEF_CR			0x6A
#define _INIT_VD_SATURATION		0x80	// for BK3.65h initial setting
#define _INIT_VD_CONTRAST			0x80		//for BK3.64h intial setting
#define _INIT_VD_CON				0x92		//for BK3.63h intial setting

#ifdef _MST7X_C_
BYTE code tPanel_InitialTable[]=
{
	0x03, BK0_25_OPL_SET0,			// Set output clock (32.5MHz)
	0x00, 0x00, 0xB2,

	0x01, BK0_36_VDSUSG,
	0x00,

	0x17, BK0_40_VFDEST_L,
	LOBYTE(PANEL_VSTART),			// VFDEST [41:40]
	HIBYTE(PANEL_VSTART),
	LOBYTE(PANEL_HSTART),			// HFDEST [43:42]
	HIBYTE(PANEL_HSTART),
	LOBYTE(PANEL_HEIGHT),			// VFDEEND [45:44]
	HIBYTE(PANEL_HEIGHT),
	LOBYTE(PANEL_HSTART+PANEL_WIDTH),	// HFDEEND [47:46]
	HIBYTE(PANEL_HSTART+PANEL_WIDTH),
	LOBYTE(PANEL_HSTART),			// SIHST [49:48]
	HIBYTE(PANEL_HSTART),
	LOBYTE(PANEL_HEIGHT),			// SIVEND [4B:4A]
	HIBYTE(PANEL_HEIGHT),
	LOBYTE(PANEL_HSTART+PANEL_WIDTH),	// SIHEND [4D:4C]
	HIBYTE(PANEL_HSTART+PANEL_WIDTH),
	LOBYTE(PANEL_VTOTAL),			// VDTOT [4F:4E]
	HIBYTE(PANEL_VTOTAL),
	0xF1,	//LOBYTE(PANEL_VTOTAL-PANEL_VSTART),	// VSST [51:50]
	0x08,	//HIBYTE(PANEL_VTOTAL-PANEL_VSTART),
	0xFE,	//LOBYTE(PANEL_VTOTAL-PANEL_VSYNC_WIDTH-PANEL_VSYNC_BACK_PORCH),	// VSEND [53:52]
	0x00,	//HIBYTE(PANEL_VTOTAL-PANEL_VSYNC_WIDTH-PANEL_VSYNC_BACK_PORCH),
	LOBYTE(PANEL_HTOTAL-1),			// HDTOT [55:54]
	HIBYTE(PANEL_HTOTAL-1),
	PANEL_HSYNC_WIDTH,			// HSEND [56]

	0x02, BK0_60_DITHCTRL,
	PANEL_DITHER_CONTROL,
	0x2D,

	0x01, BK0_86_FNTN_TEST,
	PANEL_SWAP_CONTROL,

	0x01, BK0_B1_SYNC_CONTROL,
	PANEL_SYNC_CONTROL,
	
	-1,
	
};

// ************ ACE setting start ****************

BYTE code tMsACETable[]=
{
	
	1, GEN_00_REGBK,			// select register bank ADC
	REGBANKADC,
	
	// MACE setting start
	
	// lpf 9 tap  0x50
	5, BK1_50_LPF_TAP1,
	0x7E, 0x04, 0x3C, 0x04, 0x1C,

	// wle and ble (enable)   0x7F 0x80
	2, BK1_7F_MAX_PIX,
	0xFA, 0x08,
	
	// 0x7e   03 to 02 jordan0608  solve vetical line disable white peaking
	1, BK1_7E_VIP_Y_CTRL,	
	0x03,

	// fcc	0x56-0x76
	33, BK1_56_FCC_CB_1T,
	0x70, 0x93, 0x6E, 0xAC, 0x9D, 0x6B, 0x5A, 0x9A,
	0x5D, 0x75, 0xB0, 0x48, 0x64, 0xC8, 0x80, 0x80,
	0x80, 0x80, 0xB2, 0xBA, 0xFB, 0x73, 0xFB, 0xFB,
	0xFF, 0x6A, 0x00, 0xFF, 0x40, 0x88, 0xE8, 0x85,
	0x4B,

	// lpf + (diff peak)  0x88
	1, BK1_88_YC_LPF,
	0x1C,
	
	// band 1  0x78
	1, BK1_78_PEAK_BAND1,	 
	0x9F,

	2, BK1_81_EGE_BAND1_POS,
	0x10, 0x30,
	
	// band 2  0x79
	1, BK1_79_PEAK_BAND2,
	0x5F,

	2, BK1_83_EGE_BAND2_POS,
	0x04, 0x10,
	
	// lti	0x7a
	1, BK1_7A_LTI,
	0xDA,

	2, BK1_86_EGE_LTI_POS,
	0x00, 0x00,

	3, BK1_7B_TERM_SEL,
	0xB5,		// mix term
	0x84,		// coring
	0x70,		// cti

	// enable cti_med cti lti_med lti peak lpftap (csc)   0x77
	1, BK1_77_APP_CTRL,
	0x7E,

	//bri_YPbPr   0x85
	 1, BK1_85_M_BRI,
	 0xF8,	
	
	// MACE setting end
	
	1, GEN_00_REGBK,			// select register bank scaler
	REGBANKSCALER,
	
	-1,
};


BYTE code tGammaTableNormal[3][33]=
{
	
	{
		0x00,0x03,0x08,0x0F,0x18,0x21,0x2C,0x36,0x42,0x4D,0x57,
		0x62,0x6B,0x74,0x7C,0x84,0x8C,0x94,0x9C,0xA4,0xAC,0xB3,
		0xBA,0xC2,0xC9,0xD0,0xD7,0xDE,0xE5,0xEB,0xF2,0xF8,0xFF,
	},
	{
		0x00,0x03,0x08,0x0F,0x18,0x21,0x2C,0x36,0x42,0x4D,0x57,
		0x62,0x6B,0x74,0x7C,0x84,0x8C,0x94,0x9C,0xA4,0xAC,0xB3,
		0xBA,0xC2,0xC9,0xD0,0xD7,0xDE,0xE5,0xEB,0xF2,0xF8,0xFF,
	},
	{
		0x00,0x03,0x08,0x0F,0x18,0x21,0x2C,0x36,0x42,0x4D,0x57,
		0x62,0x6B,0x74,0x7C,0x84,0x8C,0x94,0x9C,0xA4,0xAC,0xB3,
		0xBA,0xC2,0xC9,0xD0,0xD7,0xDE,0xE5,0xEB,0xF2,0xF8,0xFF,
	},
	
};

short code tVideoColorCorrectionMatrix[][3]=
{
   0x0430,-0x0032, 0x0008, 0x0030, 0x03CD, 0x0008,-0x00A2, 0x0043,
   0x0450,-0xF4E7, 0x9FCB,-0x64C3, 0x6C04,-0x7A3B, 0x623E,-0xD1D5,
  -0x0FC2, 0xBD4E, 0xC6FD,-0xF33E, 0xE935, 0x75ED,-0x768D, 0xC174,
  -0xD43C, 0x3A18,-0xE00A, 0xD6E3,-0x330C, 0x0A84,-0xB7A0, 0xF369,
};

//**************************************************************************

#else	// _MST7X_C_
extern BYTE code tMsACETable[];
extern BYTE code tGammaTableNormal[3][33];
extern short code tVideoColorCorrectionMatrix[][3];

#endif	//_MST7X_C_

#ifdef _SYNC_C_
/****************************** CVBS Timing Table ****************************/
BYTE code tSyncCVBSNTSCTable[] = 
{
	1, GEN_00_REGBK,			// select register bank scaler
	REGBANKSCALER,

	//20050921 (set bit3 to avoid BK0_1D produce wrong message for VCR) 
	1, BK0_03_IPCTRL2,		// Set Capture  
	0x88,					// BK0_03_IPCTRL2,

#if DEMODULELATOR_MODE
	
	9, BK0_05_SPRVST_L,		// Set Capture
//	0x2F, 0x00, 
	0x05, 0x00,			// BK0_05_SPRVST_L, BK0_06_SPRVST_H    //20050921 To complement V-shift due to set the BK0_03[3]
	0x63, 0x00,
	0xDA, 0x01,
	0x8A, 0x05,
	0x00,

	7, BK0_30_SRH_L,			// Set H&V scaling rate
	0x00, 0x75, 0xC5,
	0x00, 0x00, 0x90, 0x00,
		
#else

	9, BK0_05_SPRVST_L,		// Set Capture
	0x2F, 0x00, 
	0x63, 0x00,
	0xDA, 0x01,
	0x8A, 0x05,
	0x00,

	7, BK0_30_SRH_L,			// Set H&V scaling rate
	0x00, 0x75, 0xC5,
	0x00, 0x00, 0x90, 0x00,

#endif

	// 1, BK0_E5_MDCTRL,//20050921 mask for VCR
	//0x00,

	-1
};

BYTE code tSyncCVBSPALTable[] =
{
	1, GEN_00_REGBK,			// select register bank scaler
	REGBANKSCALER,

	//20050921 (set bit3 to avoid BK0_1D produce wrong message for VCR) 
	1, BK0_03_IPCTRL2,		// Set Capture  
	0x88,					// BK0_03_IPCTRL2,

#if DEMODULELATOR_MODE
	
	9, BK0_05_SPRVST_L,		// Set Capture
//	0x33, 0x00, 
	0x05, 0x00,			// BK0_05_SPRVST_L, BK0_06_SPRVST_H    //20050921 To complement V-shift due to set the BK0_03[3]
	0x6E, 0x00,
	0x3D, 0x02,
	0x78, 0x05,
	0x00,

	7, BK0_30_SRH_L,			// Set H&V scaling rate
	0x00, 0x86, 0xC5,
	0x00, 0x60, 0x93, 0x0C,
		
#else

	9, BK0_05_SPRVST_L,		// Set Capture
	0x33, 0x00, 
	0x6E, 0x00,