📄 pnl_au102_dt.h
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0xD9, 0x01,
0xF0, 0x05, //20,06
0x03,
7, BK0_30_SRH_L, // Set H&V scaling rate
0x00, 0x47, 0x89, //00,00,89
0x00, 0xD0, 0x87, 0x0C,
#endif
-1
};
BYTE code tSyncCVBSPALTable[] =
{
1, GEN_00_REGBK, // select register bank scaler
REGBANKSCALER,
//20050921 (set bit3 to avoid BK0_1D produce wrong message for VCR)
1, BK0_03_IPCTRL2, // Set Capture
0x80, // BK0_03_IPCTRL2,
#if DEMODULELATOR_MODE
9, BK0_05_SPRVST_L, // Set Capture
//0x32, 0x00,
0x2E, 0x00, // BK0_05_SPRVST_L, BK0_06_SPRVST_H //20050921 To complement V-shift due to set the BK0_03[3]
0x5F, 0x00,
0x34, 0x02,
0x70, 0x03,
0x02,
7, BK0_30_SRH_L, // Set H&V scaling rate
0x00, 0x80, 0xC5,
0x33, 0x50, 0x89, 0x0C,
#else
9, BK0_05_SPRVST_L, // Set Capture
0x37, 0x00,
0x58, 0x01, //DE
0x2E, 0x02,
0x34, 0x07, //80
0x04,
7, BK0_30_SRH_L, // Set H&V scaling rate
0x00, 0x57, 0xC9, //00,22,C9
0x33, 0x3A, 0x93, 0x0C,
#endif
-1
};
/******************************* S-VIDEO Timing Table ****************************/
BYTE code tSyncSVideoNTSCTable[] =
{
1, GEN_00_REGBK, // select register bank scaler
REGBANKSCALER,
//20050921 (set bit3 to avoid BK0_1D produce wrong message for VCR)
1, BK0_03_IPCTRL2, // Set Capture
0x80, // BK0_03_IPCTRL2,
#if DEMODULELATOR_MODE
9, BK0_05_SPRVST_L, // Set Capture
//0x2D, 0x00,
0x22, 0x00, // BK0_05_SPRVST_L, BK0_06_SPRVST_H //20050921 To complement V-shift due to set the BK0_03[3]
0x4D, 0x00,
0xD7, 0x01,
0x70, 0x03,
0x02,
7, BK0_30_SRH_L, // Set H&V scaling rate
0x00, 0x80, 0xC5,
0x00, 0xC4, 0x87, 0x0C,
#else
9, BK0_05_SPRVST_L, // Set Capture
0x20, 0x00,
0xB5, 0x00,
0xD8, 0x01,
0xF0, 0x05,
0x03,
7, BK0_30_SRH_L, // Set H&V scaling rate
0x00, 0x4F, 0x99, // 00,E2,98
0x00, 0xD4, 0x87, 0x0C,
#endif
-1
};
BYTE code tSyncSVideoPALTable[] =
{
1, GEN_00_REGBK, // select register bank scaler
REGBANKSCALER,
//20050921 (set bit3 to avoid BK0_1D produce wrong message for VCR)
1, BK0_03_IPCTRL2, // Set Capture
0x80, // BK0_03_IPCTRL2,
#if DEMODULELATOR_MODE
9, BK0_05_SPRVST_L, // Set Capture
// 0x2D, 0x00,
0x2C, 0x00, // BK0_05_SPRVST_L, BK0_06_SPRVST_H //20050921 To complement V-shift due to set the BK0_03[3]
0x51, 0x00,
0x32, 0x02,
0x70, 0x03,
0x02,
7, BK0_30_SRH_L, // Set H&V scaling rate
0x00, 0xA0, 0xC5,
0x00, 0x40, 0x89, 0x0C,
#else
9, BK0_05_SPRVST_L, // Set Capture
0x34, 0x00,
0x22, 0x01, //E0 01 //AA
0x2E, 0x02,
0x34, 0x07, // 2B 07 //97
0x04,
7, BK0_30_SRH_L, // Set H&V scaling rate
0x00, 0x58, 0xC9, //00,FA,C8
0x00, 0x40, 0x89, 0x0C,
#endif
-1
};
/******************************* VGA Timing Table ****************************/
BYTE code tSyncVGAModeTable[] =
{
1, GEN_00_REGBK, // select register bank scaler
REGBANKSCALER,
11, BK0_03_IPCTRL2, // Set Capture
0x80, 0x03,
0x24, 0x00,
0xE2, 0x00,
0xE2, 0x01,
0x0C, 0x05,
0x00,
3, BK0_0F_ASCTRL, //
0x00, 0x00, 0x00,
7, BK0_30_SRH_L, // Set H&V scaling rate
0x00, 0x00, 0xCA,
0x00, 0x00, 0x00, 0x00,
1, GEN_00_REGBK, // select register bank ADC
REGBANKADC,
2, BK1_02_PLLDIVM, // ADC sample clock setting
0x63, 0xD0,
2, BK1_10_CLKCTRL1, // ADC phase setting
0x00, 0x08,
1, GEN_00_REGBK, // select register bank scaler
REGBANKSCALER,
-1
};
/************************** Component Timing Table ***************************/
/***** Interlace input *****/
BYTE code tSyncYCbCrNTSCTable[] =
{
1, GEN_00_REGBK, // select register bank ADC
REGBANKADC, // 00h
2, BK1_02_PLLDIVM, // ADC sample clock setting
0x6B, 0x10, // BK1.02h, BK1.03h
1, GEN_00_REGBK, // select register bank scaler
REGBANKSCALER,
9, BK0_05_SPRVST_L, // Set Capture
0x2E, 0x00,
0x7A, 0x00,
0xD4, 0x01,
0x96, 0x05,
0x03,
1, BK0_0F_ASCTRL, // Line buffer
0x20, // BK0.0Fh
7, BK0_30_SRH_L, // Set H&V scaling rate
0x00, 0x30, 0xC9,
0x00, 0xC0, 0x87, 0x0C,
-1,
};
BYTE code tSyncYCbCrPALTable[] =
{
1, GEN_00_REGBK, // select register bank ADC
REGBANKADC, // 00h
2, BK1_02_PLLDIVM, // ADC sample clock setting
0x6B, 0xD0, // BK1.02h, BK1.03h
1, GEN_00_REGBK, // select register bank scaler
REGBANKSCALER,
9, BK0_05_SPRVST_L, // Set Capture
0x34, 0x00,
0x9C, 0x00,
0x32, 0x02,
0x72, 0x05,
0x04,
1, BK0_0F_ASCTRL, // Line buffer
0x20, // BK0.0Fh
7, BK0_30_SRH_L, // Set H&V scaling rate
0x00, 0x58, 0xC9,
0x00, 0x50, 0x89, 0x0C,
-1,
};
/***** Non-Interlace input *****/
BYTE code tSyncYPbPrNTSCTable[] =
{
1, GEN_00_REGBK, // select register bank ADC
REGBANKADC, // 00h
2, BK1_02_PLLDIVM, // ADC sample clock setting
0x6B, 0x10, // BK1.02h, BK1.03h
1, GEN_00_REGBK, // select register bank scaler
REGBANKSCALER,
9, BK0_05_SPRVST_L, // Set Capture
0x24, 0x00,
0x6A, 0x00,
0xE2, 0x01,
0xA8, 0x05,
0x00,
1, BK0_0F_ASCTRL, // Line buffer
0x10, // BK0.0Fh
7, BK0_30_SRH_L, // Set H&V scaling rate
0x00, 0x30, 0xC9,
0x00, 0x00, 0x00, 0x00,
-1,
};
BYTE code tSyncYPbPrPALTable[] =
{
1, GEN_00_REGBK, // select register bank ADC
REGBANKADC, // 00h
2, BK1_02_PLLDIVM, // ADC sample clock setting
0x6B, 0xD0, // BK1.02h, BK1.03h
1, GEN_00_REGBK, // select register bank scaler
REGBANKSCALER,
9, BK0_05_SPRVST_L, // Set Capture
0x28, 0x00,
0x7F, 0x00,
0x42, 0x02,
0xA8, 0x05,
0x00,
1, BK0_0F_ASCTRL, // Line buffer
0x10, // BK0.0Fh
7, BK0_30_SRH_L, // Set H&V scaling rate
0x00, 0x30, 0xC9,
0x33, 0x33, 0x93, 0x00,
-1,
};
/**************************** CCIR656 Timing Table ***************************/
BYTE code tSyncCCIRNTSCTable[] =
{
1, GEN_00_REGBK, // select register bank scaler
REGBANKSCALER,
9, BK0_05_SPRVST_L, // Set Capture
0x26, 0x00,
0x03, 0x00,
0xE5, 0x01,
0xA0, 0x05,
0x04,
7, BK0_30_SRH_L, // Set H&V scaling rate
0x00, 0x18, 0xC9,
0x00, 0x00, 0x88, 0x0C,
-1,
};
BYTE code tSyncCCIRPALTable[] =
{
1, GEN_00_REGBK, // select register bank scaler
REGBANKSCALER,
9, BK0_05_SPRVST_L, // Set Capture
0x2B, 0x00,
0x0A, 0x00,
0x44, 0x02,
0xA0, 0x05,
0x04,
7, BK0_30_SRH_L, // Set H&V scaling rate
0x00, 0x18, 0xC9,
0x99, 0x99, 0x89, 0x00,
-1,
};
#endif //_SYNC_C_
///////////////////////////////////////////////////////
// TCON setting
///////////////////////////////////////////////////////
// PTC Mode setting
#define SET_PTC_MODE1 0x8C // PTC_MODE1(0xD0)
#define SET_PTC_MODE2 0x1A // PTC_MODE2(0xD1)
#define SET_PTC_MODE3 0x82 // PTC_MODE3(0xD2)
// PTC Timming Setting
#define SET_FRP_TRAN 0x02 // GPO_FRP_TRAN(0xDC)
#define SET_STH_START 0x6F // GPO_STH_START(0xDD)
#define SET_STH_WIDTH 0x01 // GPO_STH_WIDTH(0xDE)
#define SET_OEH_START 0x6E // GPO_OEH_START(0xDF)
#define SET_OEH_WIDTH 0x07 // GPO_OEH_WIDTH(0xE0)
#define SET_OEV_START 0x6C // GPO_OEV_START(0xE1)
#define SET_OEV_WIDTH 0x29 // GPO_OEV_WIDTH(0xE2)
#define SET_CKV_START 0x6D // GPO_CKV_START(0xE3)
#define SET_CKV_START2 0x00 // GPO_CKV_START2(0xE4)
#define SET_CKV_WIDTH 0x1C // GPO_CKV_WIDTH(0xE5)
#define SET_STV_LINE_TH 0x45 // GPO_STV_LINE_TH(0xE6)
#define SET_STV_START 0x6F // GPO_STV_START(0xE7)
#define SET_STV_WIDTH 0x00 // GPO_STV_WIDTH(0xE8)
#define SET_OEV2_START 0x00 // GPO_OEV2_START(0xE9)
#define SET_OEV3_START 0x00 // GPO_OEV3_START(0xEA)
#define SET_H_ST_DLY_L 0x00 // H_ST_DLY_L(0xEB)
#define SET_H_ST_DLY_H 0x00 // H_ST_DLY_H(0xEC)
#define SET_CLK_DLY_SYNC_OUT 0x00 // CLK_DLY_SYNC_OUT(0xED)
#define SET_CKV_END2 0x00 // GPO_CKV_END2(0xEE)
#define SET_Q1H 0x00 // Q1H_SETTING(0xEF)
#define SET_OEV2_WIDTH 0x54 // GPO_OEV2_WIDTH(0xCD)
#define SET_OEV3_WIDTH 0x54 // GPO_OEV3_WIDTH(0xCE)
#define SET_OEV_DELTA 0x54 // GPO_OEV_DELTA(0xCF)
// VCOM setting
#define SET_BVOM_DC 0xEF //DEF_VCOM_DC // BVOM_DC(0x43)
#define SET_BVOM_OUT 0xFF //DEF_VCOM_AC // BVOM_OUT(0x44)
// DAC setting
#define SET_VDAC_ADJ1 0x00 // VADC_ADJ1(0xAA)
#define SET_VDAC_ADJ2 0x00 // VDAC_ADJ2(0xAB)
// Backlight PWM setting
#define SET_BACKLIGHT_PWM 0xFF // for Bk1.F4h initial setting
#endif //__AU102_H
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