📄 pnl_lg07_at.h
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/******************************************************************************
Copyright (c) 2003 MStar Semiconductor, Inc.
All rights reserved.
[Module Name]: Pnl_LG07_AT.h
[Date]: 25-Mar-2005
[Comment]:
Panel parameters.[LB070W02] 1440X234
[Reversion History]:
*******************************************************************************/
#ifndef __LG7_H
#define __LG7_H
///////////////////////////////////////////////
// Common setting
///////////////////////////////////////////////
#define PANEL_NAME "LG07_AT"
#define PANEL_DOT_WIDTH 107 // unit: um
#define PANEL_DOT_HEIGHT 370 // unit: um
//////////////////////////////////////////////
// Panel output
//////////////////////////////////////////////
#define PANEL_DITHER 1 // 8/6 bits panel
#define PANEL_LVDS 0
#define PANEL_TTL 0
#define PANEL_TCON 0
#define PANEL_ANALOG_TCON 1
#define PANEL_SWAP_LVDS_POL 0
#define PANEL_SWAP_LVDS_CH 0
#define PANEL_LVDS_TI_MODE 0
#define PANEL_6BIT_OUT 0 // 0/1: 8BIT/6BIT out
#define PANEL_DITHER_ENABLE 1 // 0/1:Enable/Disable
#define PANEL_DITHER_CONTROL 0x0C+(PANEL_6BIT_OUT<<1)+PANEL_DITHER_ENABLE
#define PANEL_SWAP_8BIT_ML 0
#define PANEL_SWAP_6BIT_ML 0
#if 0 //FSC_8X
#define PANEL_SWAP_RB 0
#else
#define PANEL_SWAP_RB 0
#endif
#define PANEL_SWAP_CONTROL (PANEL_SWAP_RB<<2)+(PANEL_SWAP_6BIT_ML<<1)+PANEL_SWAP_8BIT_ML
#define PANEL_DCLK_DELAY 0x0 // Range (0~F)
#define PANEL_INV_DCLK 1 // 1: Invert output DCLK
#define PANEL_INV_DE 0 // 1: Invert output DE
#define PANEL_INV_VSYNC 0 // 1: Invert output VSYNC
#define PANEL_INV_HSYNC 0 // 1: Invert output HSYNC
#define PANEL_SYNC_CONTROL (PANEL_DCLK_DELAY<<4)+(PANEL_INV_DCLK<<3)+(PANEL_INV_DE<<2) \
+(PANEL_INV_VSYNC<<1)+PANEL_INV_HSYNC
// Lock Y line
#define PANEL_LOCK_Y_LINE 0
///////////////////////////////////////////////
// Output tmming setting
///////////////////////////////////////////////
// driving current setting (0x00=4mA, 0x01=6mA, 0x02=8mA, 0x03=12mA)
#define PANEL_DCLK_CURRENT 0x01 // DCLK current
#define PANEL_DE_CURRENT 0x01 // DE signal current
#define PANEL_HS_CURRENT 0x01 // HSYNC current
#define PANEL_VS_CURRENT 0x01 // VSYNC current
#define PANEL_BM_CURRENT 0x01 // B data High-Nibble current
#define PANEL_BL_CURRENT 0x01 // B data Low-Nibble current
#define PANEL_GM_CURRENT 0x01 // G data High-Nibble current
#define PANEL_GL_CURRENT 0x01 // G data Low-Nibble current
#define PANEL_RM_CURRENT 0x01 // R data High-Nibble current
#define PANEL_RL_CURRENT 0x01 // R data Low-Nibble current
#define PANEL_ADCLK_CURRENT 0x01 // Analog Panel DCLK current
#define PANEL_ON_TIMING1 30 // time between panel & data while turn on power
#define PANEL_ON_TIMING2 100 // time between data & back light while turn on power
#define PANEL_OFF_TIMING1 20 // time between back light & data while turn off power
#define PANEL_OFF_TIMING2 20 // time between data & panel while turn off power
#define PANEL_HSYNC_WIDTH 20
#define PANEL_HSYNC_BACK_PORCH 35
#define PANEL_VSYNC_WIDTH 4
#define PANEL_VSYNC_BACK_PORCH 24
#define PANEL_HSTART (PANEL_HSYNC_WIDTH + PANEL_HSYNC_BACK_PORCH)
#define PANEL_VSTART 0 //(PANEL_VSYNC_WIDTH + PANEL_VSYNC_BACK_PORCH)
#define PANEL_WIDTH 480
#define PANEL_HEIGHT 234
#define PANEL_HTOTAL 654
#define PANEL_VTOTAL 300
#define PANEL_MAX_HTOTAL 1300
#define PANEL_MIN_HTOTAL 1035
#define PANEL_MAX_VTOTAL 750
#define PANEL_MIN_VTOTAL 610
#define PANEL_DCLK (((DWORD)PANEL_HTOTAL*PANEL_VTOTAL*60)/1000000)
#define PANEL_MAX_DCLK 49
#define PANEL_MIN_DCLK 39
///////////////////////////////////////////////
// Panel color default setting
///////////////////////////////////////////////
#define _COLOR_DEF_CONTRAST 115//0x5F // 95
#define _COLOR_DEF_SATURATION 128//0xAA // 170
#define _COLOR_DEF_HUE 50
#define _COLOR_DEF_CB 0x80
#define _COLOR_DEF_CR 0x80
#define _INIT_VD_SATURATION 0x80 // for BK3.65h initial setting
#define _INIT_VD_BRT 0x80 //for BK3.64h intial setting
#define _INIT_VD_CON 0x92 //for BK3.63h intial setting
#ifdef _MST7X_C_
BYTE code tPanel_InitialTable[]=
{
0x03, BK0_25_OPL_SET0, // Set output clock (32.5MHz)
0x00, 0x20, 0x3B, // BK0_25_OPL_SET0, BK0_26_OPL_SET1, BK0_27_OPL_SET2
0x01, BK0_36_VDSUSG,
0x10, // BK0_36_VDSUSG
0x17, BK0_40_VFDEST_L,
LOBYTE(PANEL_VSTART), // VFDEST [41:40]
HIBYTE(PANEL_VSTART), // BK0_40_VFDEST_L, BK0_41_VFDEST_H
LOBYTE(PANEL_HSTART), // HFDEST [43:42]
HIBYTE(PANEL_HSTART), // BK0_42_HFDEST_L, BK0_43_HFDEST_H
LOBYTE(PANEL_HEIGHT+4), // VFDEEND [45:44]
HIBYTE(PANEL_HEIGHT+4), // BK0_44_VFDEEND_L, BK0_45_VFDEEND_H
LOBYTE(PANEL_HSTART+PANEL_WIDTH-1), // HFDEEND [47:46]
HIBYTE(PANEL_HSTART+PANEL_WIDTH-1), // BK0_46_HFDEEND_L, BK0_47_HFDEEND_H
LOBYTE(PANEL_HSTART), // SIHST [49:48]
HIBYTE(PANEL_HSTART), // BK0_48_SIHST_L, BK0_49_SIHST_H
LOBYTE(PANEL_HEIGHT+4), // SIVEND [4B:4A]
HIBYTE(PANEL_HEIGHT+4), // BK0_4A_SIVEND_L, BK0_4B_SIVEND_H
LOBYTE(PANEL_HSTART+PANEL_WIDTH-1), // SIHEND [4D:4C]
HIBYTE(PANEL_HSTART+PANEL_WIDTH-1), // BK0_4C_SIHEND_L, BK0_4D_SIHEND_H
LOBYTE(PANEL_VTOTAL), // VDTOT [4F:4E]
HIBYTE(PANEL_VTOTAL), // BK0_4E_VDTOT_L, BK0_4F_VDTOT_H
// BK0_50_VSST_L, BK0_51_VSST_H, BK0_52_VSEND_L, BK0_53_VSEND_H
0xF6, //LOBYTE(PANEL_VTOTAL-PANEL_VSTART), // VSST [51:50]
0x08, //HIBYTE(PANEL_VTOTAL-PANEL_VSTART),
0xFE, //LOBYTE(PANEL_VTOTAL-PANEL_VSYNC_WIDTH-PANEL_VSYNC_BACK_PORCH), // VSEND [53:52]
0x00, //HIBYTE(PANEL_VTOTAL-PANEL_VSYNC_WIDTH-PANEL_VSYNC_BACK_PORCH),
LOBYTE(PANEL_HTOTAL-1), // HDTOT [55:54]
HIBYTE(PANEL_HTOTAL-1), // BK0_54_HDTOT_L, BK0_55_HDTOT_H
PANEL_HSYNC_WIDTH, // BK0_56_HSEND
0x02, BK0_60_DITHCTRL,
PANEL_DITHER_CONTROL, // BK0_60_DITHCTRL
0x2D, // BK0_61_DITHCOEF
0x01, BK0_86_FNTN_TEST,
PANEL_SWAP_CONTROL, // BK0_86_FNTN_TEST
0x01, BK0_B1_SYNC_CONTROL,
PANEL_SYNC_CONTROL, // BK0_B1_SYNC_CONTROL
-1,
};
// ************ ACE setting start ****************
BYTE code tMsACETable[]=
{
1, GEN_00_REGBK, // select register bank ADC
REGBANKADC, // GEN_00_REGBK
#if(MARIA_TYPE_SEL == MARIA_2)
// MACE setting start
// lpf 9 tap 0x50
6, BK1_50_LPF_TAP1, //
0x7E, 0x04, // BK1_50_LPF_TAP1, BK1_51_LPF_TAP2
0x3C, 0x04, // BK1_52_LPF_TAP3, BK1_53_LPF_TAP4
0x1C, 0x40, // BK1_54_LPF_TAP5, BK1_55,
// wle and ble (enable) 0x7F 0x80
2, BK1_7F_MAX_PIX,
0xA0, 0x40, // BK1_7F_MAX_PIX, BK1_80_MIN_PIX
// 0x7e 03 to 02 jordan0608 solve vetical line disable white peaking
1, BK1_7E_VIP_Y_CTRL,
0x02, // BK1_7E_VIP_Y_CTRL
1, BK1_A8_SET_XTAL,
0x07, // BK1_77_APP_CTRL
// fcc 0x56-0x76
33, BK1_56_FCC_CB_1T,
0x73, 0x9B, 0x6E, 0xAC, 0xA5, 0x69, 0x5A, 0x9A, // BK1_56, BK1_57, BK1_58, BK1_59, BK1_5A, BK1_5B, BK1_5C, BK1_5D,
0x5A, 0x75, 0xB0, 0x48, 0x64, 0xC8, 0x80, 0x80, // BK1_5E, BK1_5F, BK1_60, BK1_61, BK1_62, BK1_63, BK1_64, BK1_65,
0x80, 0x98, 0xB2, 0xBA, 0xFB, 0x73, 0xFB, 0xFB, // BK1_66, BK1_67, BK1_68, BK1_69, BK1_6A, BK1_6B, BK1_6C, BK1_6D,
0xFF, 0x6A, 0x00, 0xFF, 0x60, 0x8E, 0x8B, 0x85, // BK1_6E, BK1_6F, BK1_70, BK1_71, BK1_72, BK1_73, BK1_74, BK1_75,
0x4F, // BK1_76,
24, BK1_78_PEAK_BAND1,
0x1D, 0x58, 0x98, 0xE4, 0x48, 0x78, 0x02, 0x80,
0x40, 0x40, 0x60, 0x00, 0x60, 0x04, 0x10, 0x20,
0x9C, 0x00, 0x23, 0x43, 0xFF, 0xAE, 0x36, 0x01,
/*
// lpf + (diff peak) 0x88
1, BK1_88_YC_LPF,
0x0C, // BK1_88_YC_LPF
// band 1 0x78
1, BK1_78_PEAK_BAND1,
0x20, // BK1_78_PEAK_BAND1
2, BK1_81_EGE_BAND1_POS,
0xFF, 0xFF, // BK1_81_EGE_BAND1_POS, BK1_82_EGE_BAND1_NEG
// band 2 0x79
1, BK1_79_PEAK_BAND2,
0x58, // BK1_79_PEAK_BAND2
2, BK1_83_EGE_BAND2_POS,
0x30, 0x60, // BK1_83_EGE_BAND2_POS, BK1_84_EGE_BAND2_NEG
// lti 0x7a
1, BK1_7A_LTI,
0x8C, // BK1_7A_LTI
2, BK1_86_EGE_LTI_POS,
0x08, 0x10, // BK1_86_EGE_LTI_POS, BK1_87_EGE_LTI_NEG
3, BK1_7B_TERM_SEL,
0x55, // mix term BK1_7B_TERM_SEL
0x31, // coring BK1_7C_CROING
0x70, // cti BK1_7D_CTI
// enable cti_med cti lti_med lti peak lpftap (csc) 0x77
1, BK1_77_APP_CTRL,
0x7E, // BK1_77_APP_CTRL
//bri_YPbPr 0x85
1, BK1_85_M_BRI, // 0xE0 for Mode1_CSC_Bypass "1110b"
0x00, // BK1_85_M_BRI
6, BK1_8A,
0x23, 0x43, 0xFF, 0xAE, 0x36, 0x01,
// MACE setting end
*/
#else
// MACE setting start
// lpf 9 tap 0x50
5, BK1_50_LPF_TAP1,
0x7E, 0x04, // BK1_50_LPF_TAP1, BK1_51_LPF_TAP2
0x3C, 0x04, // BK1_52_LPF_TAP3, BK1_53_LPF_TAP4
0x1C, // BK1_54_LPF_TAP5
// wle and ble (enable) 0x7F 0x80
2, BK1_7F_MAX_PIX,
0xFA, 0x08, // BK1_7F_MAX_PIX, BK1_80_MIN_PIX
// 0x7e 03 to 02 jordan0608 solve vetical line disable white peaking
1, BK1_7E_VIP_Y_CTRL,
0x03, // BK1_7E_VIP_Y_CTRL
// fcc 0x56-0x76
33, BK1_56_FCC_CB_1T,
0x72, 0x93, 0x6E, 0xAC, 0x9D, 0x6B, 0x5A, 0x9A, // BK1_56, BK1_57, BK1_58, BK1_59, BK1_5A, BK1_5B, BK1_5C, BK1_5D,
0x5F, 0x75, 0xB0, 0x48, 0x64, 0xC8, 0x80, 0x80, // BK1_5E, BK1_5F, BK1_60, BK1_61, BK1_62, BK1_63, BK1_64, BK1_65,
0x80, 0x80, 0xB2, 0xBA, 0xFB, 0x73, 0xFB, 0xFB, // BK1_66, BK1_67, BK1_68, BK1_69, BK1_6A, BK1_6B, BK1_6C, BK1_6D,
0xFF, 0x6A, 0x00, 0xFF, 0x40, 0x88, 0x88, 0x85, // BK1_6E, BK1_6F, BK1_70, BK1_71, BK1_72, BK1_73, BK1_74, BK1_75,
0x4B, // BK1_76,
// lpf + (diff peak) 0x88
1, BK1_88_YC_LPF,
0x1C, // BK1_88_YC_LPF
// band 1 0x78
1, BK1_78_PEAK_BAND1,
0xEA, // BK1_78_PEAK_BAND1
2, BK1_81_EGE_BAND1_POS,
0x10, 0x30, // BK1_81_EGE_BAND1_POS, BK1_82_EGE_BAND1_NEG
// band 2 0x79
1, BK1_79_PEAK_BAND2,
0x5F, // BK1_79_PEAK_BAND2
2, BK1_83_EGE_BAND2_POS,
0x04, 0x10, // BK1_83_EGE_BAND2_POS, BK1_84_EGE_BAND2_NEG
// lti 0x7a
1, BK1_7A_LTI,
0xDA, // BK1_7A_LTI
2, BK1_86_EGE_LTI_POS,
0x00, 0x00, // BK1_86_EGE_LTI_POS, BK1_87_EGE_LTI_NEG
3, BK1_7B_TERM_SEL,
0xB5, // mix term BK1_7B_TERM_SEL
0x84, // coring BK1_7C_CROING
0x70, // cti BK1_7D_CTI
// enable cti_med cti lti_med lti peak lpftap (csc) 0x77
1, BK1_77_APP_CTRL,
0x7E, // BK1_77_APP_CTRL
//bri_YPbPr 0x85
1, BK1_85_M_BRI, // 0xE0 for Mode1_CSC_Bypass "1110b"
0xE0, // BK1_85_M_BRI
// MACE setting end
#endif
1, GEN_00_REGBK, // select register bank scaler
REGBANKSCALER, // GEN_00_REGBK
-1,
};
BYTE code tGammaTableNormal[3][33]=
{
{
0x00,0x06,0x0D,0x15,0x23,0x36,0x4A,0x58,0x64,0x6C,0x74,
0x79,0x7F,0x84,0x8A,0x90,0x97,0x9D,0xA2,0xA7,0xAC,0xB1,
0xB6,0xBC,0xC2,0xC8,0xCF,0xD6,0xDF,0xE7,0xEF,0xF7,0xFF,
},
{
0x00,0x06,0x0D,0x15,0x23,0x36,0x4A,0x58,0x64,0x6C,0x74,
0x79,0x7F,0x84,0x8A,0x90,0x97,0x9D,0xA2,0xA7,0xAC,0xB1,
0xB6,0xBC,0xC2,0xC8,0xCF,0xD6,0xDF,0xE7,0xEF,0xF7,0xFF,
},
{
0x00,0x06,0x0D,0x15,0x23,0x36,0x4A,0x58,0x64,0x6C,0x74,
0x79,0x7F,0x84,0x8A,0x90,0x97,0x9D,0xA2,0xA7,0xAC,0xB1,
0xB6,0xBC,0xC2,0xC8,0xCF,0xD6,0xDF,0xE7,0xEF,0xF7,0xFF,
},
};
short code tVideoColorCorrectionMatrix[][3]=
{
0x040D,-0x0010, 0x0002, 0x0012, 0x03C1, 0x002D, 0x002F,-0x0031,
0x0402,-0xC04F, 0x448C,-0x0CA1, 0xC501,-0xCBE8, 0xA849,-0xB3E7,
-0xF638, 0xE7E0, 0x96E5,-0x60EF, 0x4D2A, 0x98A9,-0x165C, 0x79F5,
-0xA54C, 0x862A,-0x367E, 0x4969,-0x9BA8, 0xFC3D,-0x856F, 0x7B72,
};
//**************************************************************************
#else // _MST7X_C_
extern BYTE code tMsACETable[];
extern BYTE code tGammaTableNormal[3][33];
extern short code tVideoColorCorrectionMatrix[][3];
#endif //_MST7X_C_
#ifdef _SYNC_C_
/****************************** CVBS Timing Table ****************************/
BYTE code tSyncCVBSNTSCTable[] =
{
1, GEN_00_REGBK, // select register bank scaler
REGBANKSCALER,
//20050921 (set bit3 to avoid BK0_1D produce wrong message for VCR)
1, BK0_03_IPCTRL2, // Set Capture
0x80, // BK0_03_IPCTRL2,
#if DEMODULELATOR_MODE
9, BK0_05_SPRVST_L, // Set Capture
#if ((MARIA_TYPE_SEL == MARIA_2) && ENABLE_VD_DSP)
0x1D, 0x00, // BK0_05_SPRVST_L, BK0_06_SPRVST_H
#else
0x27, 0x00, // BK0_05_SPRVST_L, BK0_06_SPRVST_H //20050921 To complement V-shift due to set the BK0_03[3]
#endif
0x3A, 0x00, // BK0_07_SPRHST_L, BK0_08_SPRHST_H
0xE0, 0x01,
0xFC, 0x02, // BK0_0B_SPRHDC_L, BK0_0C_SPRHDC_H
0x00,
7, BK0_30_SRH_L, // Set H&V scaling rate
0x00, 0x80, 0xC5, // BK0_30_SRH_L, BK0_31_SRH_M, BK0_32_SRH_H
0x00, 0x00, 0x90, 0x10, // BK0_33_SRV_L, BK0_34_SRV_M, BK0_35_SRV_H, BK0_36_VDSUSG
#else
9, BK0_05_SPRVST_L, // Set Capture
0x24, 0x00,
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