📄 pnl_au07_at.h
字号:
9, BK0_05_SPRVST_L, // Set Capture
0x25, 0x00, // BK0_05_SPRVST_L, BK0_06_SPRVST_H
0xEF, 0x00, // BK0_07_SPRHST_L, BK0_08_SPRHST_H
0xD8, 0x01, // BK0_09_SPRVDC_L, BK0_0A_SPRVDC_H
0xF0, 0x05, // BK0_0B_SPRHDC_L, BK0_0C_SPRHDC_H
0x00, // BK0_0D_LYL
7, BK0_30_SRH_L, // Set H&V scaling rate
0x00, 0x20, 0xC5, // BK0_30_SRH_L, BK0_31_SRH_M, BK0_32_SRH_H
0x00, 0x00, 0x90, 0x1C, // BK0_33_SRV_L, BK0_34_SRV_M, BK0_35_SRV_H, BK0_36_VDSUSG
#endif
-1
};
BYTE code tSyncCVBSPALTable[] =
{
1, GEN_00_REGBK, // select register bank scaler
REGBANKSCALER,
//20050921 (set bit3 to avoid BK0_1D produce wrong message for VCR)
1, BK0_03_IPCTRL2, // Set Capture
0x80, // BK0_03_IPCTRL2,
#if DEMODULELATOR_MODE
9, BK0_05_SPRVST_L, // Set Capture
#if ((MARIA_TYPE_SEL == MARIA_2) && ENABLE_VD_DSP)
0x1A, 0x00, // BK0_05_SPRVST_L, BK0_06_SPRVST_H
#else
0x31, 0x00, // BK0_05_SPRVST_L, BK0_06_SPRVST_H //20050921 To complement V-shift due to set the BK0_03[3]
#endif
0x49, 0x00, // BK0_07_SPRHST_L, BK0_08_SPRHST_H
0x46, 0x02, // BK0_09_SPRVDC_L, BK0_0A_SPRVDC_H
0xE0, 0x02, // BK0_0B_SPRHDC_L, BK0_0C_SPRHDC_H
0x00, // BK0_0D_LYL
7, BK0_30_SRH_L, // Set H&V scaling rate
0x00, 0x80, 0xC5, // BK0_30_SRH_L, BK0_31_SRH_M, BK0_32_SRH_H
0x33, 0x3A, 0x93, 0x1C, // BK0_33_SRV_L, BK0_34_SRV_M, BK0_35_SRV_H, BK0_36_VDSUSG
#else
9, BK0_05_SPRVST_L, // Set Capture
0x30, 0x00, // BK0_05_SPRVST_L, BK0_06_SPRVST_H
0x58, 0x01, // BK0_07_SPRHST_L, BK0_08_SPRHST_H
0x38, 0x02, // BK0_09_SPRVDC_L, BK0_0A_SPRVDC_H
0x34, 0x07, // BK0_0B_SPRHDC_L, BK0_0C_SPRHDC_H
0x00, // BK0_0D_LYL
7, BK0_30_SRH_L, // Set H&V scaling rate
0x00, 0x40, 0xC4, // BK0_30_SRH_L, BK0_31_SRH_M, BK0_32_SRH_H
0x33, 0x3A, 0x93, 0x1C, // BK0_33_SRV_L, BK0_34_SRV_M, BK0_35_SRV_H, BK0_36_VDSUSG
#endif
-1
};
/***************************** S-VIDEO Timing Table **************************/
BYTE code tSyncSVideoNTSCTable[] =
{
1, GEN_00_REGBK, // select register bank scaler
REGBANKSCALER,
//20050921 (set bit3 to avoid BK0_1D produce wrong message for VCR)
1, BK0_03_IPCTRL2, // Set Capture
0x88, // BK0_03_IPCTRL2,
#if DEMODULELATOR_MODE
9, BK0_05_SPRVST_L, // Set Capture
//0x2A, 0x00, // BK0_05_SPRVST_L, BK0_06_SPRVST_H
0x1D, 0x00, // BK0_05_SPRVST_L, BK0_06_SPRVST_H //20050921 To complement V-shift due to set the BK0_03[3]
0x2D, 0x00, // BK0_07_SPRHST_L, BK0_08_SPRHST_H
0xE6, 0x01, // BK0_09_SPRVDC_L, BK0_0A_SPRVDC_H
0xFC, 0x02, // BK0_0B_SPRHDC_L, BK0_0C_SPRHDC_H
0x00, // BK0_0D_LYL
7, BK0_30_SRH_L, // Set H&V scaling rate
0x00, 0x80, 0xC5, // BK0_30_SRH_L, BK0_31_SRH_M, BK0_32_SRH_H
0x00, 0x00, 0x90, 0x1C, // BK0_33_SRV_L, BK0_34_SRV_M, BK0_35_SRV_H, BK0_36_VDSUSG
#else
9, BK0_05_SPRVST_L, // Set Capture
0x20, 0x00, // BK0_05_SPRVST_L, BK0_06_SPRVST_H
0xB9, 0x00, // BK0_07_SPRHST_L, BK0_08_SPRHST_H
0xD8, 0x01, // BK0_09_SPRVDC_L, BK0_0A_SPRVDC_H
0xF0, 0x05, // BK0_0B_SPRHDC_L, BK0_0C_SPRHDC_H
0x00, // BK0_0D_LYL
7, BK0_30_SRH_L, // Set H&V scaling rate
0x00, 0x40, 0xC5, // BK0_30_SRH_L, BK0_31_SRH_M, BK0_32_SRH_H
0x00, 0x00, 0x90, 0x1C, // BK0_33_SRV_L, BK0_34_SRV_M, BK0_35_SRV_H, BK0_36_VDSUSG
#endif
-1
};
BYTE code tSyncSVideoPALTable[] =
{
1, GEN_00_REGBK, // select register bank scaler
REGBANKSCALER,
//20050921 (set bit3 to avoid BK0_1D produce wrong message for VCR)
1, BK0_03_IPCTRL2, // Set Capture
0x88, // BK0_03_IPCTRL2,
#if DEMODULELATOR_MODE
9, BK0_05_SPRVST_L, // Set Capture
//0x2C, 0x00, // BK0_05_SPRVST_L, BK0_06_SPRVST_H
0x28, 0x00, // BK0_05_SPRVST_L, BK0_06_SPRVST_H //20050921 To complement V-shift due to set the BK0_03[3]
0x3E, 0x00, // BK0_07_SPRHST_L, BK0_08_SPRHST_H
0x46, 0x02, // BK0_09_SPRVDC_L, BK0_0A_SPRVDC_H
0xE0, 0x02, // BK0_0B_SPRHDC_L, BK0_0C_SPRHDC_H
0x00, // BK0_0D_LYL
7, BK0_30_SRH_L, // Set H&V scaling rate
0x00, 0x80, 0xC5, // BK0_30_SRH_L, BK0_31_SRH_M, BK0_32_SRH_H
0x33, 0x3A, 0x93, 0x1C, // BK0_33_SRV_L, BK0_34_SRV_M, BK0_35_SRV_H, BK0_36_VDSUSG
#else
9, BK0_05_SPRVST_L, // Set Capture
0x2E, 0x00, // BK0_05_SPRVST_L, BK0_06_SPRVST_H
0x22, 0x01, // BK0_07_SPRHST_L, BK0_08_SPRHST_H
0x38, 0x02, // BK0_09_SPRVDC_L, BK0_0A_SPRVDC_H
0x34, 0x07, // BK0_0B_SPRHDC_L, BK0_0C_SPRHDC_H
0x00, // BK0_0D_LYL
7, BK0_30_SRH_L, // Set H&V scaling rate
0x00, 0x40, 0xC4, // BK0_30_SRH_L, BK0_31_SRH_M, BK0_32_SRH_H
0x33, 0x3A, 0x93, 0x1C, // BK0_33_SRV_L, BK0_34_SRV_M, BK0_35_SRV_H, BK0_36_VDSUSG
#endif
-1
};
/******************************* VGA Timing Table ****************************/
BYTE code tSyncVGAModeTable[] =
{
1, GEN_00_REGBK, // select register bank scaler
REGBANKSCALER,
11, BK0_03_IPCTRL2, // Set Capture
0x98, 0x03, // BK0_03_IPCTRL2, BK0_04_ISCTRL
0x1E, 0x00, // BK0_05_SPRVST_L, BK0_06_SPRVST_H
0x81, 0x00, // BK0_07_SPRHST_L, BK0_08_SPRHST_H seven 051018
0xE3, 0x01, // BK0_09_SPRVDC_L, BK0_0A_SPRVDC_H
0x0F, 0x05, // BK0_0B_SPRHDC_L, BK0_0C_SPRHDC_H
0x00, // BK0_0D_LYL
3, BK0_0F_ASCTRL,
0x00, 0x00, 0x00, // BK0_0F_ASCTRL, BK0_10_COCTRL1, BK0_11_COCTRL2
7, BK0_30_SRH_L, // Set H&V scaling rate
0x00, 0x00, 0xC6, // BK0_30_SRH_L, BK0_31_SRH_M, BK0_32_SRH_H
0x00, 0x00, 0xA0, 0x1C, // BK0_33_SRV_L, BK0_34_SRV_M, BK0_35_SRV_H, BK0_36_VDSUSG
1, GEN_00_REGBK, // select register bank ADC
REGBANKADC,
2, BK1_02_PLLDIVM, // ADC sample clock setting
0x63, 0xD0, // BK1_02_PLLDIVM, BK1_03_PLLDIVL
2, BK1_10_CLKCTRL1, // ADC phase setting
0x00, 0x08, // BK1_10_CLKCTRL1, BK1_11_CLKCTRL2
1, GEN_00_REGBK, // select register bank scaler
REGBANKSCALER,
-1
};
/************************** Component Timing Table ***************************/
/***** Interlace input *****/
BYTE code tSyncYCbCrNTSCTable[] =
{
1, GEN_00_REGBK, // select register bank ADC
REGBANKADC, // 00h
2, BK1_02_PLLDIVM, // ADC sample clock setting
0x6B, 0x10, // BK1_02_PLLDIVM, BK1_03_PLLDIVL
1, GEN_00_REGBK, // select register bank scaler
REGBANKSCALER,
9, BK0_05_SPRVST_L, // Set Capture
0x07, 0x00, // BK0_05_SPRVST_L, BK0_06_SPRVST_H
0x80, 0x00, // BK0_07_SPRHST_L, BK0_08_SPRHST_H
0xF0, 0x01, // BK0_09_SPRVDC_L, BK0_0A_SPRVDC_H
0xA8, 0x05, // BK0_0B_SPRHDC_L, BK0_0C_SPRHDC_H
0x00, // BK0_0D_LYL
1, BK0_0F_ASCTRL, // Line buffer
0x10, // BK0_0F_ASCTRL
7, BK0_30_SRH_L, // Set H&V scaling rate
0x00, 0x30, 0xC9, // BK0_30_SRH_L, BK0_31_SRH_M, BK0_32_SRH_H
0x00, 0xBC, 0x87, 0x1C, // BK0_33_SRV_L, BK0_34_SRV_M, BK0_35_SRV_H, BK0_36_VDSUSG
-1,
};
BYTE code tSyncYCbCrPALTable[] =
{
1, GEN_00_REGBK, // select register bank ADC
REGBANKADC, // 00h
2, BK1_02_PLLDIVM, // ADC sample clock setting
0x6B, 0xD0, // BK1_02_PLLDIVM, BK1_03_PLLDIVL
1, GEN_00_REGBK, // select register bank scaler
REGBANKSCALER,
9, BK0_05_SPRVST_L, // Set Capture
0x12, 0x00, // BK0_05_SPRVST_L, BK0_06_SPRVST_H
0xA8, 0x00, // BK0_07_SPRHST_L, BK0_08_SPRHST_H
0x58, 0x02, // BK0_09_SPRVDC_L, BK0_0A_SPRVDC_H
0xA8, 0x05, // BK0_0B_SPRHDC_L, BK0_0C_SPRHDC_H
0x00, // BK0_0D_LYL
1, BK0_0F_ASCTRL, // Line buffer
0x10, // BK0_0F_ASCTRL
7, BK0_30_SRH_L, // Set H&V scaling rate
0x00, 0x58, 0xC9, // BK0_30_SRH_L, BK0_31_SRH_M, BK0_32_SRH_H
0x00, 0x58, 0x89, 0x1C, // BK0_33_SRV_L, BK0_34_SRV_M, BK0_35_SRV_H, BK0_36_VDSUSG
-1,
};
/***** Non-Interlace input *****/
BYTE code tSyncYPbPrNTSCTable[] =
{
1, GEN_00_REGBK, // select register bank ADC
REGBANKADC, // 00h
2, BK1_02_PLLDIVM, // ADC sample clock setting
0x6B, 0x10, // BK1_02_PLLDIVM, BK1_03_PLLDIVL
1, GEN_00_REGBK, // select register bank scaler
REGBANKSCALER,
9, BK0_05_SPRVST_L, // Set Capture
0x04, 0x00, // BK0_05_SPRVST_L, BK0_06_SPRVST_H
0x6A, 0x00, // BK0_07_SPRHST_L, BK0_08_SPRHST_H
0xF0, 0x01, // BK0_09_SPRVDC_L, BK0_0A_SPRVDC_H
0xA8, 0x05, // BK0_0B_SPRHDC_L, BK0_0C_SPRHDC_H
0x00, // BK0_0D_LYL
1, BK0_0F_ASCTRL, // Line buffer
0x10, // BK0_0F_ASCTRL
7, BK0_30_SRH_L, // Set H&V scaling rate
0x00, 0x30, 0xC9, // BK0_30_SRH_L, BK0_31_SRH_M, BK0_32_SRH_H
0x00, 0x90, 0x8F, 0x1C, // BK0_33_SRV_L, BK0_34_SRV_M, BK0_35_SRV_H, BK0_36_VDSUSG
-1,
};
BYTE code tSyncYPbPrPALTable[] =
{
1, GEN_00_REGBK, // select register bank ADC
REGBANKADC, // 00h
2, BK1_02_PLLDIVM, // ADC sample clock setting
0x6B, 0xD0, // BK1_02_PLLDIVM, BK1_03_PLLDIVL
1, GEN_00_REGBK, // select register bank scaler
REGBANKSCALER,
9, BK0_05_SPRVST_L, // Set Capture
0x07, 0x00, // BK0_05_SPRVST_L, BK0_06_SPRVST_H
0x98, 0x00, // BK0_07_SPRHST_L, BK0_08_SPRHST_H
0x58, 0x02, // BK0_09_SPRVDC_L, BK0_0A_SPRVDC_H
0xA8, 0x05, // BK0_0B_SPRHDC_L, BK0_0C_SPRHDC_H
0x00, // BK0_0D_LYL
1, BK0_0F_ASCTRL, // Line buffer
0x10, // BK0_0F_ASCTRL
7, BK0_30_SRH_L, // Set H&V scaling rate
0x00, 0xC0, 0xC9, // BK0_30_SRH_L, BK0_31_SRH_M, BK0_32_SRH_H
0x00, 0xC8, 0x92, 0x1C, // BK0_33_SRV_L, BK0_34_SRV_M, BK0_35_SRV_H, BK0_36_VDSUSG
-1,
};
/**************************** CCIR656 Timing Table ***************************/
BYTE code tSyncCCIRNTSCTable[] =
{
1, GEN_00_REGBK, // select register bank scaler
REGBANKSCALER,
9, BK0_05_SPRVST_L, // Set Capture
0x31, 0x00, // BK0_05_SPRVST_L, BK0_06_SPRVST_H
0x96, 0x00, // BK0_07_SPRHST_L, BK0_08_SPRHST_H
0xE7, 0x01, // BK0_09_SPRVDC_L, BK0_0A_SPRVDC_H
0xB8, 0x02, // BK0_0B_SPRHDC_L, BK0_0C_SPRHDC_H
0x00, // BK0_0D_LYL
7, BK0_30_SRH_L, // Set H&V scaling rate
0x00, 0x18, 0xCB, // BK0_30_SRH_L, BK0_31_SRH_M, BK0_32_SRH_H
0x00, 0x00, 0x90, 0x1C, // BK0_33_SRV_L, BK0_34_SRV_M, BK0_35_SRV_H, BK0_36_VDSUSG
-1,
};
BYTE code tSyncCCIRPALTable[] =
{
1, GEN_00_REGBK, // select register bank scaler
REGBANKSCALER,
9, BK0_05_SPRVST_L, // Set Capture
0x33, 0x00, // BK0_05_SPRVST_L, BK0_06_SPRVST_H
0x9D, 0x00, // BK0_07_SPRHST_L, BK0_08_SPRHST_H
0x48, 0x02, // BK0_09_SPRVDC_L, BK0_0A_SPRVDC_H
0xB8, 0x02, // BK0_0B_SPRHDC_L, BK0_0C_SPRHDC_H
0x00, // BK0_0D_LYL
7, BK0_30_SRH_L, // Set H&V scaling rate
0x00, 0x00, 0xCB, // BK0_30_SRH_L, BK0_31_SRH_M, BK0_32_SRH_H
0x00, 0x50, 0x93, 0x1C, // BK0_33_SRV_L, BK0_34_SRV_M, BK0_35_SRV_H, BK0_36_VDSUSG
-1,
};
#endif //_SYNC_C_
///////////////////////////////////////////////////////
// TCON setting
///////////////////////////////////////////////////////
// PTC Mode setting
#define SET_PTC_MODE1 0x8E // PTC_MODE1(BK1_D0_PTC_MODE1)
#if ((BOARD_TYPE_SEL == BD_DEMO_7918MA_IAP)||(BOARD_TYPE_SEL == BD_DEMO_7988M_IAP)||(BOARD_TYPE_SEL == BD_DEMO_7988LR_IAP)||(BOARD_TYPE_SEL == BD_EXMCU_7988M_IAP))//kevin
#define SET_PTC_MODE2 0x3E // PTC_MODE2(BK1_D1_PTC_MODE2)
#elif (BOARD_TYPE_SEL == BD_SOCKET_7988LR_IAP)
#define SET_PTC_MODE2 0x32
#else
#define SET_PTC_MODE2 0x36 // PTC_MODE2(BK1_D1_PTC_MODE2)
#endif
#define SET_PTC_MODE3 0x81 // PTC_MODE3(BK1_D2_PTC_MODE3)
// PTC Timming Setting
#define SET_FRP_TRAN 0x13 // GPO_FRP_TRAN(BK1_DC_GPO_FRP_TRAN)
#define SET_STH_START 0x2D // GPO_STH_START(BK1_DD_GPO_STH_STT) ORG:0x2C
#define SET_STH_WIDTH 0x01 // GPO_STH_WIDTH(BK1_DE_GPO_STH_WIDTH)
#define SET_OEH_START 0x88 // GPO_OEH_START(BK1_DF_GPO_OEH_STT)
#define SET_OEH_WIDTH 0x0B // GPO_OEH_WIDTH(BK1_E0_GPO_OEH_WIDTH)
#define SET_OEV_START 0x03 // GPO_OEV_START(BK1_E1_GPO_OEV_STT)
#define SET_OEV_WIDTH 0x2A // GPO_OEV_WIDTH(BK1_E2_GPO_OEV_WIDTH)
#define SET_CKV_START 0x28 // GPO_CKV_START(BK1_E3_GPO_CKV_STT)
#define SET_CKV_START2 0x00 // GPO_CKV_START2(BK1_E4_GPO_CKV_STT2)
#define SET_CKV_WIDTH 0x2A // GPO_CKV_WIDTH(BK1_E5_GPO_CKV_WIDTH)
#define SET_STV_LINE_TH 0x42 // GPO_STV_LINE_TH(BK1_E6_GPO_STV_LN_TH)
#define SET_STV_START 0x00 // GPO_STV_START(BK1_E7_GPO_STV_STT)
#define SET_STV_WIDTH 0x00 // GPO_STV_WIDTH(BK1_E8_GPO_STV_WIDTH)
#define SET_OEV2_START 0x04 // GPO_OEV2_START(BK1_E9_GPO_OEV2_STT)
#define SET_OEV3_START 0x04 // GPO_OEV3_START(BK1_EA_GPO_OEV3_STT)
#define SET_H_ST_DLY_L 0x04 // H_ST_DLY_L(BK1_EB_HSTT_DLY_L)
#define SET_H_ST_DLY_H 0xA4 // H_ST_DLY_H(BK1_EC_HSTT_DLY_H)
#define SET_CLK_DLY_SYNC_OUT 0x00 // CLK_DLY_SYNC_OUT(BK1_ED_CLK_DLY_SYNC_OUT)
#define SET_CKV_END2 0x28 // GPO_CKV_END2(BK1_EE_GPO_CKV_END2)
#define SET_Q1H 0x00 // Q1H_SETTING(BK1_EF_Q1H_SETTING)
#define SET_OEV2_WIDTH 0x54 // GPO_OEV2_WIDTH(BK1_CD_GPO_OEV2_WIDTH)
#define SET_OEV3_WIDTH 0x54 // GPO_OEV3_WIDTH(BK1_CE_GPO_OEV3_WIDTH)
#define SET_OEV_DELTA 0x54 // GPO_OEV_DELTA(BK1_CF_GPO_OEV_DELTA)
// VCOM setting
#define SET_BVOM_DC 0x96 //0xA0 //DEF_VCOM_DC // BK1_43_BVOM_DC
#define SET_BVOM_OUT 0xB0 //0x80 //DEF_VCOM_AC // BK1_44_BVOM_OUT
// DAC setting
#define SET_VDAC_ADJ1 0x47 // VADC_ADJ1(BK1_AA_VDAC_ADJ1)
#define SET_VDAC_ADJ2 0x00 // VDAC_ADJ2(BK1_AB_VDAC_ADJ2)
// Backlight PWM setting
#define SET_BACKLIGHT_PWM 0xB0 // for BK1_F4_PWM1C initial setting
#endif // __AU7_H
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