📄 sync.h

📁 MST720-DEMO程序
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/******************************************************************************
 Copyright (c) 2005 MStar Semiconductor, Inc.
 All rights reserved.

 [Module Name]: Sync.h
 [Date]:	16-Feb-2005
 [Comment]:
   Header file for Sync.c module..
 [Reversion History]:
*******************************************************************************/

#ifndef _SYNC_H_
#define _SYNC_H_

#ifdef _SYNC_C_
#define _SYNCDEC_
#else
#define _SYNCDEC_	extern
#endif

/********************
* INCLUDE FILES          *
*********************/
#include "TypeDef.h"

/********************
* LOCAL MACROS	       *
*********************/
// for "g_ucSyncStatus" flag define
#define VSYNC_NEGATIVE_B		_BIT0
#define HSYNC_NEGATIVE_B		_BIT1
#define DEMODULATION_MODE1_B	_BIT2
#define INTERLANCE_MODE_B		_BIT3
#define CSYNC_MODE_B			_BIT4
#define PAL_MODE_B				_BIT5
#define NO_HSYNC_B				_BIT6
#define NO_VSYNC_B				_BIT7
#define SYNC_LOSS_MASK			(NO_HSYNC_B+NO_VSYNC_B)

#define SYNC_CHECK_TIMES		20
#define SYNC_STABLE_TIMES		10	// 3+2

/********************
* STATIC DATA	       *
*********************/
#ifdef _SYNC_C_
BYTE code tSyncCVBSTable[] = 
{
// select register bank scaler (BANK0)
//===============================================================
	1, GEN_00_REGBK,			// select register bank 0 scaler
	REGBANKSCALER,			// 00h

	1, BK0_02_ISELECT,		// Mute Display
	0x8C,				// BK0_02_ISELECT

	2, BK0_03_IPCTRL2,		// Set Capture
	0x80, 0x10,			// BK0_03_IPCTRL2, BK0_04_ISCTRL

	4, BK0_0F_ASCTRL,		//
#if (PANEL_WIDTH <= 500) 
	0x10, 0x20, 0x00, 0x00,		// BK0_0F_ASCTRL, BK0_10_COCTRL1, BK0_11_COCTRL2, BK0_12_COCTRL3
#else	// (PANEL_WIDTH <= 500)
	0x20, 0x20, 0x00, 0x00,		// BK0_0F_ASCTRL, BK0_10_COCTRL1, BK0_11_COCTRL2, BK0_12_COCTRL3
#endif	// (PANEL_WIDTH <= 500)

#if (MARIA_TYPE_SEL == MARIA_2 && PANEL_WIDTH >= 720)
	1, BK0_37,
	0x01,
#endif

	4, BK0_58_BRIGHTNESS_EN,	// digital Brightness setting
	0x01, 0x7F, 0x83, 0x80,		// BK0.58h, BK0.59h, BK0.5Ah, BK0.5Bh

	1, BK0_76_COL_MATRIX_CTL,	// color matrix control
	0x35,				// BK0_76_COL_MATRIX_CTL

#if (MARIA_TYPE_SEL == MARIA_2)
	6, BK0_E0_PDMD0,			// power down and interlance control
	0x00, 0x00, 0x00,			// BK0_E0_PDMD0, BK0_E1_PDMD1, BK0_E2_SWRST0
	//kevin mask for full odd filed //0x00, 0x00, 0x00,			// BK0.E3h, BK0.E4h, BK0.E5h
	//20050921 only set Bk0_E5[2] to avoid image tremble for VCR
#if 0 // ENABLE_VD_DSP
	0x00, 0x03, 0x04,			// BK0_E3_SWRST1, BK0_E4_ISOVRD, BK0_E5_MDCTRL 
#else
	0x00, 0x03, 0x00,			// BK0_E3_SWRST1, BK0_E4_ISOVRD, BK0_E5_MDCTRL 
#endif

#else
	6, BK0_E0_PDMD0,			// power down and interlance control
	0x00, 0x00, 0x00,			// BK0_E0_PDMD0, BK0_E1_PDMD1, BK0_E2_SWRST0
	//kevin mask for full odd filed //0x00, 0x00, 0x00,			// BK0.E3h, BK0.E4h, BK0.E5h
	//20050921 only set Bk0_E5[2] to avoid image tremble for VCR
	0x00, 0x03, 0x04,			// BK0_E3_SWRST1, BK0_E4_ISOVRD, BK0_E5_MDCTRL 
#endif
// select register bank ADC (BANK1)
//===============================================================
	1, GEN_00_REGBK,			// select register bank 1 ADC
	REGBANKADC,			// 00h

	2, BK1_02_PLLDIVM,		// ADC sample clock setting
	0x41, 0xD0,			// BK1_02_PLLDIVM, BK1_03_PLLDIVL

	3, BK1_07_ROFFS_ADC,		// ADC offset setting
	0x11, 0x11, 0x11,			// BK1_07_ROFFS_ADC, BK1_08_GOFFS_ADC, BK1_09_BOFFS_ADC

	2, BK1_10_CLKCTRL1,		// ADC phase setting
	0x08, 0x00,			// BK1_10_CLKCTRL1, BK1_11_CLKCTRL2

	1, BK1_1F_ADC_ICTRL,		// video performace improvement setting
	0x55,//20050908 kevin //0x15,				// BK1_10_CLKCTRL1

	2, BK1_24_FPLL_MD,		// FPLL control for CVBS
	0x40, 0x01,			// BK1_24_FPLL_MD, BK1_25_FPLL_DIVN

	1, BK1_2B,			// 
	0x1C,				// BK1_2B

#if (MARIA_TYPE_SEL == MARIA_2)
	1, BK1_22_TESTD2,
	0x40,
	
	1, BK1_29,			// R.G.BENCADC for CVBS
	0x1F,				// BK1_29

	1, BK1_34,			// Vclamp voltage
	0x10,				// BK1_34
	
	1, BK1_9C,
	0x03,
#else
	
	1, BK1_29,			// R.G.BENCADC for CVBS
	0x0F,				// BK1_29

	1, BK1_34,			// Vclamp voltage
	0x30,				// BK1_34
#endif

// select register bank VFE (BANK2)
//===============================================================
	1, GEN_00_REGBK,			// select register bank 2 VFE
	REGBANKVFE,			// 00h,

	1, BK2_17_FSC_SEL,
	0xF9,				// BK2_17_FSC_SEL
	
	1, BK2_22_APLL_CTRL3,		// Clamp enable
	0xC6,				// BK2_22_APLL_CTRL3

	4, BK2_5B_FSC443_357DECT5,				
	0x9F, 0x9F, 0x48, 0x24,		// BK2_5B, BK2_5C, BK2_5D, Bk2_5E

#if (MARIA_TYPE_SEL == MARIA_2)
	1, BK2_2F_BLACK_SEL,
	0x81,

#if (PANEL_WIDTH > 1100)
	1, BK2_79_656_HDES1,
	0x18,

//	1, BK2_7B_656_HDEW,
//	0xE0,

	2, BK2_9D_DPL_NSPL_HIGH,
	0xC7, 0x00,

#elif (PANEL_WIDTH > 900)

	1, BK2_79_656_HDES1,
	0x18,

//	1, BK2_7B_656_HDEW,
//	0xE0,

	2, BK2_9D_DPL_NSPL_HIGH,
	0xAA, 0x80,


#elif (PANEL_WIDTH > 720)
	1, BK2_79_656_HDES1,
	0x18,

//	1, BK2_7B_656_HDEW,
//	0xE0,

	2, BK2_9D_DPL_NSPL_HIGH,
	0x85, 0xA0,
	
#else
	1, BK2_79_656_HDES1,
	0x18,
	
//	1, BK2_7B_656_HDEW,
//	0xD0,
	
	2, BK2_9D_DPL_NSPL_HIGH,
	0x71, 0xC0,			// ORG. 0x71, 0xA0 modify for PAL-M signal 
	
#endif
#endif
// select register bank scaler (BANK0)
//===============================================================
	1, GEN_00_REGBK,			// select register bank 0 scaler
	REGBANKSCALER,			// 00h

	-1
};

BYTE code tSyncRGBTable[] = 
{
// select register bank scaler (BANK0)
//===============================================================
	1, GEN_00_REGBK,			// select register bank 0 scaler
	REGBANKSCALER,			// 00h

	1, BK0_02_ISELECT,		// Mute Display
	0x84,				// BK0_02_ISELECT

	2, BK0_03_IPCTRL2,		// Set Capture
	0x80, 0x03,			// BK0_03_IPCTRL2, BK0_04_ISCTRL
	
	4, BK0_0F_ASCTRL,		// 
	0x00, 0x00, 0x00, 0x00,			// BK0_0F_ASCTRL, BK0_10_COCTRL1, BK0_11_COCTRL2, BK0_12_COCTRL3

#if (MARIA_TYPE_SEL == MARIA_2)
	1, BK0_37,
	0x00,
#endif

	4, BK0_58_BRIGHTNESS_EN,	// digital Brightness setting
	0x00, 0xD0, 0xD0, 0xD0,		//BK0_58_BRIGHTNESS_EN, BK0_59_BRI_R, BK0_5A_BRI_G, BK0_5B_BRI_B

	1, BK0_76_COL_MATRIX_CTL,	// color matrix control
	0x00,				// BK0_76_COL_MATRIX_CTL

	6, BK0_E0_PDMD0,			// power down and interlance control
	0x00, 0x00, 0x00, 			// BK0_E0_PDMD0, BK0_E1_PDMD1, BK0_E2_SWRST0
	0x00, 0x00, 0x04,			// BK0_E3_SWRST1, BK0_E4_ISOVRD, BK0_E5_MDCTRL
	
// select register bank ADC (BANK1)
//===============================================================
	1, GEN_00_REGBK,			// select register bank 1 ADC
	REGBANKADC,			// 00h

	3, BK1_07_ROFFS_ADC,		// ADC offset setting
	0x80, 0x80, 0x80,			// BK1_07_ROFFS_ADC, BK1_08_GOFFS_ADC, BK1_09_BOFFS_ADC

	1, BK1_1F_ADC_ICTRL,		// video performace improvement setting
	0x55,//20050908 kevin //0x15,				// BK1_10_CLKCTRL1

	2, BK1_24_FPLL_MD,		// FPLL control for RGB
	0x50, 0x00,			// BK1_24_FPLL_MD, BK1_25_FPLL_DIVN

	1, BK1_2B,			// 
	0x3C,				// BK1_2B

#if (MARIA_TYPE_SEL == MARIA_2)
	1, BK1_22_TESTD2,
	0x40,
	
	1, BK1_29,			// R.G.BENCADC for RGB
	0x18,				// BK1_29
	
	1, BK1_34,			// Vclamp voltage
	0x10,				// BK1_34

	
	1, BK1_9C,
	0x03,
#else
	1, BK1_29,			// R.G.BENCADC for RGB
	0x08,				// BK1_29
	
	1, BK1_34,			// Vclamp voltage
	0x30,				// BK1_34
#endif


// select register bank VFE (BANK2)
//===============================================================
	1, GEN_00_REGBK,			// select register bank 2 VFE
	REGBANKVFE,			// 00h

	1, BK2_17_FSC_SEL,
	0xC9,				// BK2_17_FSC_SEL
	
	1, BK2_22_APLL_CTRL3,		// Clamp enable
	0x66,				// BK2_22_APLL_CTRL3
	
	4, BK2_5B_FSC443_357DECT5,				
	0x8F, 0x8F, 0x08, 0x60,		// BK2_5B, BK2_5C, BK2_5D, Bk2_5E

// select register bank scaler (BANK0)
//===============================================================
	1, GEN_00_REGBK,			// select register bank 0 scaler
	REGBANKSCALER,			// 00h
	
	-1
};

BYTE code tSyncYCbCrTable[] =
{
// select register bank scaler (BANK0)
//===============================================================
	1, GEN_00_REGBK,			// select register bank 0 scaler
	REGBANKSCALER,			// 00h

	1, BK0_02_ISELECT,		// Mute Display
	0x9C,				// BK0_02_ISELECT

	2, BK0_03_IPCTRL2,		// Set Capture
	0x90, 0x02,			// BK0_03_IPCTRL2, BK0_04_ISCTRL

	4, BK0_0F_ASCTRL,		// 
#if (PANEL_WIDTH <= 500)
	0x30, 0x21, 0x10, 0x10,			// BK0_0F_ASCTRL, BK0_10_COCTRL1, BK0_11_COCTRL2, BK0_12_COCTRL3
#else	// (PANEL_WIDTH <= 500)
	0x20, 0x21, 0x10, 0x10,			// BK0_0F_ASCTRL, BK0_10_COCTRL1, BK0_11_COCTRL2, BK0_12_COCTRL3
#endif	// (PANEL_WIDTH <= 500)

#if (MARIA_TYPE_SEL == MARIA_2)
	1, BK0_37,
	0x00,
#endif

	4, BK0_58_BRIGHTNESS_EN,	// digital Brightness setting
	0x00, 0x70, 0x70, 0x70,		// BK0_58_BRIGHTNESS_EN, BK0_59_BRI_R, BK0_5A_BRI_G, BK0_5B_BRI_B

	1, BK0_76_COL_MATRIX_CTL,	// color matrix control
	0x35,				// BK0_76_COL_MATRIX_CTL

	6, BK0_E0_PDMD0,			// power down and interlance control
	0x00, 0x00, 0x00, 			// BK0_E0_PDMD0, BK0_E1_PDMD1, BK0_E2_SWRST0
	0x00, 0x00, 0x00,			// BK0_E3_SWRST1, BK0_E4_ISOVRD, BK0_E5_MDCTRL
	
// select register bank ADC (BANK1)
//===============================================================
	1, GEN_00_REGBK,			// select register bank 1 ADC
	REGBANKADC,			// 00h

	6, BK1_04_RGAIN_ADC,		// ADC gain and offset setting
	0x80, 0x80, 0x80,			// BK1_04_RGAIN_ADC, BK1_05_GGAIN_ADC, BK1_06_BGAIN_ADC
	0x80, 0x80, 0x80,			// BK1_07_ROFFS_ADC, BK1_08_GOFFS_ADC, BK1_09_BOFFS_ADC

	2, BK1_10_CLKCTRL1,		// ADC phase setting
	0x08, 0x00,			// BK1_10_CLKCTRL1, BK1_11_CLKCTRL2

	1, BK1_1F_ADC_ICTRL,		// video performace improvement setting
	0x55,//20050908 kevin //0x15,				// BK1_10_CLKCTRL1

	2, BK1_24_FPLL_MD,		// FPLL control for RGB
	0x54, 0x00,			// BK1_24_FPLL_MD, BK1_25_FPLL_DIVN

	1, BK1_2B,			// 
	0x3C,				// BK1_2B

#if (MARIA_TYPE_SEL == MARIA_2)
	1, BK1_22_TESTD2,
	0x40,
	
	1, BK1_29,			// R.G.BENCADC for RGB
	0x18,				// BK1_29
	
	1, BK1_34,			// Vclamp voltage
	0x10,				// BK1_34

	1, BK1_9C,
	0x03,
#else
	1, BK1_29,			// R.G.BENCADC for RGB
	0x08,				// BK1_29
	
	1, BK1_34,			// Vclamp voltage
	0x30,				// BK1_34
#endif


// select register bank VFE (BANK2)
//===============================================================
	1, GEN_00_REGBK,			// select register bank 2 VFE
	REGBANKVFE,			// 00h

	1, BK2_17_FSC_SEL,
	0xC9,				// BK2_17_FSC_SEL
	
	1, BK2_22_APLL_CTRL3,		// Clamp enable
	0x66,				// BK2_22_APLL_CTRL3
	
	4, BK2_5B_FSC443_357DECT5,				
	0x8F, 0x8F, 0x08, 0x60,		// BK2_5B, BK2_5C, BK2_5D, BK2_.5E

// select register bank scaler (BANK0)
//===============================================================
	1, GEN_00_REGBK,			// select register bank 0 scaler
	REGBANKSCALER,			// 00h

	-1
};

BYTE code tSyncCCIRTable[] = 
{
	
// select register bank scaler (BANK0)
//===============================================================
	1, GEN_00_REGBK,			// select register bank 0 scaler
	REGBANKSCALER,			// 00h


	1, BK0_02_ISELECT,		// Mute Display
	0x8D,				// BK0_02_ISELECT
	
#if (MARIA_TYPE_SEL == MARIA_2)
	2, BK0_03_IPCTRL2,		// Set Capture
	0x00, 0x00, 		// BK0_03_IPCTRL2, BK0_04_ISCTRL
#else
	2, BK0_03_IPCTRL2,		// Set Capture
	0x98, 0x00,			// BK0_03_IPCTRL2, BK0_04_ISCTRL
#endif

	4, BK0_0F_ASCTRL,		// 
	0x10, 0x20, 0x00, 0x00,		// BK0_0F_ASCTRL, BK0_10_COCTRL1, BK0_11_COCTRL2, BK0_12_COCTRL3

#if (MARIA_TYPE_SEL == MARIA_2 && PANEL_WIDTH >= 720)
	1, BK0_37,
	0x01,
#endif

	1, BK0_76_COL_MATRIX_CTL,	// color matrix control
	0x35,				// BK0_76_COL_MATRIX_CTL

	6, BK0_E0_PDMD0,			// power down and interlance control
	0x00, 0x00, 0x00,			// BK0_E0_PDMD0, BK0_E1_PDMD1, BK0_E2_SWRST0
	0x00, 0x00, 0x04,			// BK0_E3_SWRST1, BK0_E4_ISOVRD, BK0_E5_MDCTRL

	-1
};

// Demodulation Mode 1
/*************************** NTSC(443) Timing Table **************************/
BYTE code tSyncCVBSNTSC443Table[] =
{
	1, GEN_00_REGBK,			// select register bank scaler
	REGBANKSCALER,

	4, BK0_05_SPRVST_L,		// Set Capture
	0x2D, 0x00,			// BK0_05_SPRVST_L, BK0_06_SPRVST_H
	0xBB, 0x00,			// BK0_07_SPRHST_L, BK0_08_SPRHST_H

	3, BK0_0B_SPRHDC_L,
	0xA0, 0x05,			// BK0_0B_SPRHDC_L, BK0_0C_SPRHDC_H
	0x03,				// BK0_0D_LYL

	-1
};

BYTE code tSyncSVideoNTSC443Table[] =
{
	1, GEN_00_REGBK,			// select register bank scaler
	REGBANKSCALER,

	4, BK0_05_SPRVST_L,		// Set Capture
	0x2D, 0x00,			// BK0_05_SPRVST_L, BK0_06_SPRVST_H 
	0x99, 0x00,			// BK0_07_SPRHST_L, BK0_08_SPRHST_H

	3, BK0_0B_SPRHDC_L,
	0xA0, 0x05,			// BK0_0B_SPRHDC_L, BK0_0C_SPRHDC_H
	0x03,				// BK0_0D_LYL

	-1
};

#endif	// _SYNC_C_
/********************
* VARIABLEV DEFINE    *
*********************/
_SYNCDEC_ BYTE g_ucSyncStableCounter;
_SYNCDEC_ BYTE g_ucSyncStatus;
_SYNCDEC_ BIT g_bVCRMode;	//20050921 for VCR
_SYNCDEC_ BIT g_bAllOddFiled;
_SYNCDEC_ BIT g_bFSC443;	//20050930 for PAL-N or NTSC-443
_SYNCDEC_ BYTE g_ucVDStatus;

#if ((MARIA_TYPE_SEL == MARIA_2) && ENABLE_VD_DSP)
_SYNCDEC_ BIT g_bEnableVDDSP;
#endif

/**********************
* FUNCTION PROTOTYPES *
***********************/
_SYNCDEC_ void mstSyncDemodulationModeSet(BIT bMode);
_SYNCDEC_ void mstSyncSourceSwitch(void);
_SYNCDEC_ void mstSyncCVBSModeSet(BYTE ucSyncStatus);
_SYNCDEC_ void mstSyncSVideoModeSet(BYTE ucSyncStatus);
_SYNCDEC_ void mstSyncVGAModeSet(BYTE ucSyncStatus);
_SYNCDEC_ void mstSyncYPbPrModeSet(BYTE ucSyncStatus);
_SYNCDEC_ void mstSyncCCIRModeSet(BYTE ucSyncStatus);
_SYNCDEC_ void mstSyncCheckSignal(void);
_SYNCDEC_ BYTE mstSyncDetect(void);
_SYNCDEC_ void mstSyncChangeHandler(void);
#if(MARIA_TYPE_SEL == MARIA_1)
_SYNCDEC_ void mstSyncVDGainHandler(BIT bFlag);
_SYNCDEC_ void mstHTotalCalibrateHandle(void);
#endif
_SYNCDEC_ void mstPatchFullOddField(void);//kevin

#if 0 //(MARIA_TYPE_SEL == MARIA_2)	// 20050930 Antony
_SYNCDEC_ void mstVDSetupMode(BOOL bFSC443);
#endif

#if(ENABLE_VD_COLOR_DETECT)
#define VD_COLOR_BURST_HANDLER_RESET _BIT7
_SYNCDEC_ BIT g_bVDColorBurstHandler_LastColorBurstStatus;
_SYNCDEC_ XDATA BYTE g_ucVDColorBurstHandlerStableCounter;
_SYNCDEC_ XDATA BYTE g_ucVDColorBurstHandlerTimer;
_SYNCDEC_ void mstVDColorKill(BOOL bColorKill);
_SYNCDEC_ void mstVDColorBurstHandler(BYTE ucFlag);
#endif


#endif	//_SYNC_H_
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