📄 ms7x_reg.h
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#define BK1_28_FPLL_TEST_L 0x28
#define BK1_29 0x29
#define BK1_2A 0x2A
#define BK1_2B 0x2B
#define BK1_2C_RGB_BW_SEL1 0x2C
#define BK1_2D_RGB_BW_SEL2 0x2D
#define BK1_2E 0x2E
#define BK1_2F_ADC_MUX 0x2F
#define BK1_30 0x30
#define BK1_31 0x31
#define BK1_32 0x32
#define BK1_33 0x33
#define BK1_34 0x34
#define BK1_35 0x35
#define BK1_36 0x36
#define BK1_37_BADCREF 0x37
#define BK1_38 0x38
#define BK1_39 0x39
#define BK1_3A 0x3A
#define BK1_3B 0x3B
#define BK1_3C 0x3C
#define BK1_3D 0x3D
#define BK1_3E 0x3E
#define BK1_3F 0x3F
#define BK1_40 0x40
#define BK1_41 0x41
#define BK1_42 0x42
#define BK1_43_BVOM_DC 0x43 // Tune ucVCOMdc (2v~1.255V)
#define BK1_44_BVOM_OUT 0x44 // Tune VCOM_OUT (0.74v~2.22V)
#define BK1_45 0x45
#define BK1_46 0x46
#define BK1_47_C_BUCK 0x47
#define BK1_48_C_CP 0x48
#define BK1_49 0x49
#define BK1_4A 0x4A
#define BK1_4B 0x4B
#define BK1_4C 0x4C
#define BK1_4D 0x4D
#define BK1_4E 0x4E
#define BK1_4F 0x4F
#define BK1_50_LPF_TAP1 0x50 // [5:0]:LPF Coefficient 1
#define BK1_51_LPF_TAP2 0x51 // [5:0]:LPF Coefficient 2
#define BK1_52_LPF_TAP3 0x52 // [5:0]:LPF Coefficient 3
#define BK1_53_LPF_TAP4 0x53 // [5:0]:LPF Coefficient 4
#define BK1_54_LPF_TAP5 0x54 // [5:0]:LPF Coefficient 5
#define BK1_55 0x55
#define BK1_56_FCC_CB_1T 0x56 // FCC Cb 1T
#define BK1_57_FCC_CR_1T 0x57 // FCC Cr 1T
#define BK1_58_FCC_CB_2T 0x58 // FCC Cb 2T
#define BK1_59_FCC_CR_2T 0x59 // FCC Cr 2T
#define BK1_5A_FCC_CB_3T 0x5A // FCC Cb 3T
#define BK1_5B_FCC_CR_3T 0x5B // FCC Cr 3T
#define BK1_5C_FCC_CB_4T 0x5C // FCC Cb 4T
#define BK1_5D_FCC_CR_4T 0x5D // FCC Cr 4T
#define BK1_5E_FCC_CB_5T 0x5E // FCC Cb 5T
#define BK1_5F_FCC_CR_5T 0x5F // FCC Cr 5T
#define BK1_60_FCC_CB_6T 0x60 // FCC Cb 6T
#define BK1_61_FCC_CR_6T 0x61 // FCC Cr 6T
#define BK1_62_FCC_CB_7T 0x62 // FCC Cb 7T
#define BK1_63_FCC_CR_7T 0x63 // FCC Cr 7T
#define BK1_64_FCC_CB_8T 0x64 // FCC Cb 8T
#define BK1_65_FCC_CR_8T 0x65 // FCC Cr 8T
#define BK1_66_FCC_CB_9T 0x66 // FCC Cb 9T
#define BK1_67_FCC_CR_9T 0x67 // FCC Cr 9T
#define BK1_68_FCC_WIN1 0x68 // [1:0]:Cr D1D;[3:2]:Cr D1U;[5:4]:Cb D1D;[7:6]:Cb D1U
#define BK1_69_FCC_WIN2 0x69 // [1:0]:Cr D2D;[3:2]:Cr D2U;[5:4]:Cb D2D;[7:6]:Cb D2U
#define BK1_6A_FCC_WIN3 0x6A // [1:0]:Cr D3D;[3:2]:Cr D3U;[5:4]:Cb D3D;[7:6]:Cb D3U
#define BK1_6B_FCC_WIN4 0x6B // [1:0]:Cr D4D;[3:2]:Cr D4U;[5:4]:Cb D4D;[7:6]:Cb D4U
#define BK1_6C_FCC_WIN5 0x6C // [1:0]:Cr D5D;[3:2]:Cr D5U;[5:4]:Cb D5D;[7:6]:Cb D5U
#define BK1_6D_FCC_WIN6 0x6D // [1:0]:Cr D6D;[3:2]:Cr D6U;[5:4]:Cb D6D;[7:6]:Cb D6U
#define BK1_6E_FCC_WIN7 0x6E // [1:0]:Cr D7D;[3:2]:Cr D7U;[5:4]:Cb D7D;[7:6]:Cb D7U
#define BK1_6F_FCC_WIN8 0x6F // [1:0]:Cr D8D;[3:2]:Cr D8U;[5:4]:Cb D8D;[7:6]:Cb D8U
#define BK1_70_FCC_WIN9 0x70 // [1:0]:Cr D9D;[3:2]:Cr D9U
#define BK1_71_FCC_Y_TH 0x71 // FCC Y Threshold
#define BK1_72_FCC_K1K2 0x72 // [3:0]:FCC K T2;[7:4]:FCC K T1
#define BK1_73_FCC_K3K4 0x73 // [3:0]:FCC K T4;[7:4]:FCC K T3
#define BK1_74_FCC_K5K6 0x74 // [3:0]:FCC K T6;[7:4]:FCC K T5
#define BK1_75_FCC_K7K8 0x75 // [3:0]:FCC K T8;[7:4]:FCC K T7
#define BK1_76_FCC_CTRL 0x76
#define M_FCC_T1_T2_B _BIT0 // FCC T1 and T2 Enable
#define M_FCC_T3_B _BIT1 // FCC T3 Enable
#define M_FCC_T4_B _BIT2 // FCC T4 Enable
#define M_FCC_T5_B _BIT3 // FCC T5 Enable
#define M_FCC_T6_B _BIT4 // FCC T6 Enable
#define M_FCC_T7_B _BIT5 // FCC T7 Enable
#define M_FCC_T8_B _BIT6 // FCC T8 Enable
#define M_FCC_T9_B _BIT7 // FCC T9 Enable
#define BK1_77_APP_CTRL 0x77
#define CSC_EN_B _BIT0 // CSC Enable
#define LPFTAP_EN_B _BIT1 // LPFTAP Enable
#define MPEN_B _BIT2 // Peak Enable
#define MLEN_B _BIT3 // LTI Enable
#define MLME_B _BIT4 // LTI_MED Enable
#define MCEN_B _BIT5 // CTI Enable
#define MCME_B _BIT6 // CTI_MED Enable
#define BK1_78_PEAK_BAND1 0x78 // [5:0]:Band 1 Coefficient;[7:6]:Band 1 Step
#define BK1_79_PEAK_BAND2 0x79 // [5:0]:Band 2 Coefficient;[7:6]:Band 2 Step
#define BK1_7A_LTI 0x7A // [5:0]:LTI Coefficient;[7:6]:LTI Step
#define BK1_7B_TERM_SEL 0x7B // Peaking Select
#define BK1_7C_CROING 0x7C // Coring Threshold
#define BK1_7D_CTI 0x7D // [4:0]:CTI Coefficient;[6:5]:CTI Step
#define BK1_7E_VIP_Y_CTRL 0x7E
#define MBLEEN_B _BIT0 // BLE Enable
#define MWLEEN_B _BIT1 // WLE Enable
#define BK1_7F_MAX_PIX 0x7F // [7:0]:Max Pixel
#define BK1_80_MIN_PIX 0x80 // [5:0]:Min Pixel
#define BK1_81_EGE_BAND1_POS 0x81 // Edge Band 1 Coefficient (positive threshold)
#define BK1_82_EGE_BAND1_NEG 0x82 // Edge Band 1 Coefficient (negaitive threshold)
#define BK1_83_EGE_BAND2_POS 0x83 // Edge Band 2 Coefficient (positive threshold)
#define BK1_84_EGE_BAND2_NEG 0x84 // Edge Band 2 Coefficient (negaitive threshold)
#define BK1_85_M_BRI 0x85 // Main window Brightness
#define BK1_86_EGE_LTI_POS 0x86 // Edge LTI Coefficient (positive threshold)
#define BK1_87_EGE_LTI_NEG 0x87 // Edge LTI Coefficient (negaitive threshold)
#define BK1_88_YC_LPF 0x88
#define B2DEN_B _BIT2 // Band 2 differentiate enable
#define B1DEN_B _BIT3 // Band 1 differentiate enable
#define Y_LPF_MD_Mask 0x30 // [5:4]:Y LPF mode
#define C_LPF_MD_Mask 0xC0 // [7:6]:C LPF mode
#define BK1_89 0x89
#define BK1_8A 0x8A
#define BK1_8B 0x8B
#define BK1_8C 0x8C
#define BK1_8D 0x8D
#define BK1_8E 0x8E
#define BK1_8F 0x8F
#define BK1_90_SARADC_CTRL 0x90
#define SAR_CH_SEL_Mask 0x03 // [1:0]:Channel selection in single channel mode
#define SAR_SINGLE_B _BIT4 // Enable single channel mode
#define SAR_FREERUN_B _BIT5 // SARADC sample mode 1/0:freerun/one shot mode
#define SAR_PD_B _BIT6 // SARADC power down
#define SAR_START_B _BIT7 // SARADC sample start (W) ready(R)
#define BK1_91_SARADC_SAMPRD 0x91 // SARADC input sample period in one shot mode
#define BK1_92_SARADC_AISEL 0x92 // [3:0]:Input select of PAD_SAR_GPIO 0/1:Digital/Analog
#define BK1_93_SARADC_TEST 0x93
#define BK1_94_SAR_CH1_UPB 0x94 // [5:0]:The voltage upper bound in MCU sleep mode for Channel 1 keypad wake up
#define BK1_95_SAR_CH1_LOB 0x95 // [5:0]:The voltage lower bound in MCU sleep mode for Channel 1 keypad wake up
#define BK1_96_SAR_CH2_UPB 0x96 // [5:0]:The voltage upper bound in MCU sleep mode for Channel 2 keypad wake up
#define BK1_97_SAR_CH2_LOB 0x97 // [5:0]:The voltage lower bound in MCU sleep mode for Channel 2 keypad wake up
#define BK1_98_SAR_CH3_UPB 0x98 // [5:0]:The voltage upper bound in MCU sleep mode for Channel 3 keypad wake up
#define BK1_99_SAR_CH3_LOB 0x99 // [5:0]:The voltage lower bound in MCU sleep mode for Channel 3 keypad wake up
#define BK1_9A 0x9A
#define BK1_9B 0x9B
#define BK1_9C 0x9C
#define BK1_9D 0x9D
#define BK1_9E 0x9E
#define BK1_9F 0x9F
#define BK1_A0_RG_DRV 0xA0
//[1:0] Pad R[3:0] driving select
//[3:2] Pad R[7:4] driving select
//[5:4] Pad G[3:0] driving select
//[7:6] Pad G[7:4] driving select
#define BK1_A1_BS_DRV 0xA1
//[1:0] Pad B[3:0] driving select
//[3:2] Pad B[7:4] driving select
//[5:4] Pad Vsync driving select
//[7:6] Pad Hsync driving select
#define BK1_A2_CTR_DRV 0xA2
//[1:0] Pad DE driving select
//[3:2] Pad CLK driving select
//[5:4] Pad PWM1 driving select
//[7:6] Pad PWM2 driving select
#define BK1_A3_EPD_R 0xA3 // Enable pull down R channel
#define BK1_A4_EPD_G 0xA4 // Enable pull down G channel
#define BK1_A5_EPD_B 0xA5 // Enable pull down B channel
#define BK1_A6_EPD_CTRL 0xA6
#define EPD_VS _BIT0 // Enable pull down in VS pad
#define EPD_HS _BIT1 // Enable pull down in HS pad
#define EPD_DE _BIT2 // Enable pull down in DE pad
#define EPD_CLK _BIT3 // Enable pull down in CLK pad
#define EPD_PWM1 _BIT4 // Enable pull down in PWM1 pad
#define EPD_PWM2 _BIT5 // Enable pull down in PWM2 pad
#define BK1_A7_PD_HSIN 0xA7
#define BK1_A8_SET_XTAL 0xA8
#define BK1_A9_PD_VDAC 0xA9
#define PD_ALL_B _BIT0 // Power down all
#define PD_R_B _BIT1 // Power down R channel
#define PD_G_B _BIT2 // Power down G channel
#define PD_B_B _BIT3 // Power down B channel
#define BK1_AA_VDAC_ADJ1 0xAA
#define BK1_AB_VDAC_ADJ2 0xAB
#define BK1_AC_EN_CDAC 0xAC
#define EN_ALL_B _BIT0 // Enable all
#define EN_R_B _BIT1 // Enable R channel
#define EN_G_B _BIT2 // Enable G channel
#define EN_B_B _BIT3 // Enable B channel
#define EN_SVM_B _BIT4 // Enable SVM channel
#define BGT_B _BIT5 //
#define BK1_AD 0xAD
#define BK1_AE 0xAE
#define BK1_AF 0xAF
#define BK1_B0_SVMCTL0 0xB0
#define SMTE_B _BIT6 // SVM Main window Tap Enable
#define SMEN_B _BIT7 // SVM Main window Enable
#define SMFT_Mask 0x30 // [5:4]:SVM Main window Filter Tap
#define BK1_B1_SVMCTL1 0xB1
#define SCORING_Mask 0x0F // [3:0]:SVM Coring
#define SVMBYS_Mask 0x30 // [5:4]:SVM Bypass Y Select
#define SINV_B _BIT6 // SMV polarity Invert
#define OSDY_B _BIT7 // OSD color Space; 1:YUV color space
#define BK1_B2_SVMLMT 0xB2 // SVM Limit
#define BK1_B3_SMSG 0xB3
#define SMGAIN_Mask 0x0F // [3:0]:SVM Main window Gain
#define SMSTEP_Mask 0x70 // [6:4]:SVM Main window Step
#define BK1_B4_SVMADJ 0xB4
#define SVMDLY_Mask 0x1F // [4:0]:SVM Delay adjust
#define SVMPIP_Mask 0x60 // [6:5]:SVM pipe adjust
#define BK1_B5_OVERLAP_SEL 0xB5
#define SVM_SD_DLY_Mask 0x1F // [4:0]:SVM Slow down delay
#define OVERLAP_SEL_Mask 0x60 // [6:5]:Overlap Select
#define SVM_SEP_DLY_B _BIT7 // SVM Separate Delay Enable
#define BK1_B6_LCK_THR_FPLL 0xB6 // Lock threshold
#define BK1_B7_LMT_LPLL_OFST_L 0xB7 // Limit lpll offset L
#define BK1_B8_LMT_LPLL_OFST_H 0xB8 // Limit lpll offset H
#define BK1_B9_COEF_FPLL 0xB9
// [3:0] Tune coeff RK
// [7:4] Tune coeff
#define BK1_BA_RK_HOLD_GAIN_L 0xBA // [7:0]:Rk hold gain L
#define BK1_BB_RK_HOLD_GAIN_H 0xBB // [3:0]:Rk hold gain H
#define BK1_BC 0xBC
#define BK1_BD 0xBD
#define BK1_BE_LPLL_STLMT_L 0xBE // Fpll set limit L
#define BK1_BF_LPLL_STLMT_H 0xBF // Fpll set limit H
#define BK1_C0_TUNE_FRAME_NO 0xC0
#define TUNE_FRAME_NO_Mask 0x03 // Frame pll tune times
#define BOND_OVER_WRITE_EN_B _BIT7 // Bonding over write enable
#define BK1_C1_BND_RST 0xC1 // Bonding reset
#define BK1_C2_LMT_ADD_NMB 0xC2 // Limit adjust number in acc_fpll mode
#define BK1_C3_IVS_DIFF_THR 0xC3 // Input VS different threshold
#define BK1_C4_IVS_STALBE_THR 0xC4 // Input VS stable threshold
#define BK1_C5_CH_CH_MODE 0xC5
#define BK1_C6_ACC1_SEL 0xC6
#define BK1_C7_IVS_PRD_NUM_L 0xC7 // [7:0]:Count number per input VS low byte
#define BK1_C8_IVS_PRD_NUM_H 0xC8 // [3:0]:Count number per input VS high 4bits
#define BK1_C9 0xC9
#define BK1_CA 0xCA
#define BK1_CB 0xCB
#define BK1_CC 0xCC
// TCON signal control
#define BK1_CD_GPO_OEV2_WIDTH 0xCD
#define BK1_CE_GPO_OEV3_WIDTH 0xCE
#define BK1_CF_GPO_OEV_DELTA 0xCF
#define BK1_D0_PTC_MODE1 0xD0
#define LINE_SHIFT_B _BIT0 // Enable Field line shift
#define FIELD_SELECT_B _BIT1 // Select field inverse from ip
#define EARLY_VS_B _BIT2 // Early vs
#define FRAME_INV_EN_B _BIT4 // Frame inverse enable
#define DOU_EXTR_MODE_Mask 0x30 // [5:4]:
#define TC_MODE_B _BIT7 // Enable TC signal output
#define BK1_D1_PTC_MODE2 0xD1
#define U_D_B _BIT0 // U_D
#define L_R_B _BIT1 // L_R
#define STVLR_SEL_B _BIT2 // 0/1:STVR/STVL
#define STHLR_SEL_B _BIT3 // 0/1:STHR/STHL
#define TCCLK_MODE_B _BIT4 // Select 3 tc clk or 1 tc clk
#define SEQ_MODE_B _BIT5 // Clock output mode 0/1:single clock/three clock
#define TCCLK_INV_B _BIT6 // Enable 3clk invverse
#define TCCLK_CONF_B _BIT7 // Enable 13 clk swap
#define BK1_D2_PTC_MODE3 0xD2
#define FRP_VCOM_INV_B _BIT0 // VCOM inverse to FRP
#define LINE_INV_DISABLE_B _BIT1 // Disable Line inverse
#define FIELD_IN_SELECT_B _BIT2 // Select field source
#define OEV2_EN_B _BIT3 // Enable OEV2(Duplicate 2/3 line mode)
#define OEV3_EN_B _BIT4 // Enable OEV3(Duplicate 2/3 line mode)
#define DF_EXT_LINE_B _BIT5 // Enable Different frame, different extract line mode
#define LG_MODE_B _BIT6 // Enable LG panel mode
#define SET_TCCLK23_VALUE_B _BIT7 // Set tcclk23 High/Low
#define BK1_D3_LN_EXTR_CNT_LMT 0xD3
//[7:4]:LINE_MXTR_CNT_LIMIT2[3:0] Line extract/duplicatte counter2
//[3:0]:LINE_MXTR_CNT_LIMIT1[3:0] Line extract/duplicatte counter1
#define BK1_D4_LN_EXTR_SET1_H 0xD4 // Line extract/duplicatte set1 high byte
#define BK1_D5_LN_EXTR_SET1_L 0xD5 // Line extract/duplicatte set1 low byte
#define BK1_D6_LN_EXTR_SET2_H 0xD6 // Line extract/duplicatte set2 high byte
#define BK1_D7_LN_EXTR_SET2_L 0xD7 // Line extract/duplicatte set2 low byte
#define BK1_D8_EXTR_STT_LN1 0xD8 // Line extract/duplicatte start line 1
#define BK1_D9_EXTR_END_LN1 0xD9 // Line extract/duplicatte end line 1
#define BK1_DA_EXTR_STT_LN2 0xDA // Line extract/duplicatte start line 2
#define BK1_DB_EXTR_END_LN2 0xDB // Line extract/duplicatte end line 2
#define BK1_DC_GPO_FRP_TRAN 0xDC // [6:0]:FRP transition position;[7]:Output invert
#define BK1_DD_GPO_STH_STT 0xDD // [6:0]:STH pulse start position;[7]:Output invert
#define BK1_DE_GPO_STH_WIDTH 0xDE // [5:0]:STH pulse width
#define BK1_DF_GPO_OEH_STT 0xDF // [6:0]:OEH pulse start position;[7]:Output invert
#define BK1_E0_GPO_OEH_WIDTH 0xE0 // [5:0]:OEH pulse width
#define BK1_E1_GPO_OEV_STT 0xE1 // [6:0]:OEV pulse start position;[7]:Output invert
#define BK1_E2_GPO_OEV_WIDTH 0xE2 // [5:0]:OEV pulse width
#define BK1_E3_GPO_CKV_STT 0xE3 // [6:0]:CKV pulse start position;[7]:Output invert
#define BK1_E4_GPO_CKV_STT2 0xE4 // [5:0]:CKV pulse start2 position
#define BK1_E5_GPO_CKV_WIDTH 0xE5 // [6:0]:CKV pulse width
#define BK1_E6_GPO_STV_LN_TH 0xE6 // [5:0]:STV line position; [6]:STV width is 1 line
#define BK1_E7_GPO_STV_STT 0xE7 // [6:0]:STV pulse start position;[7]:Output invert
#define BK1_E8_GPO_STV_WIDTH 0xE8 // [5:0]:STV pulse width
#define BK1_E9_GPO_OEV2_STT 0xE9
#define BK1_EA_GPO_OEV3_STT 0xEA
#define BK1_EB_HSTT_DLY_L 0xEB
#define BK1_EC_HSTT_DLY_H 0xEC
#define BK1_ED_CLK_DLY_SYNC_OUT 0xED // [3:0]:Tcclk delay selsect
#define BK1_EE_GPO_CKV_END2 0xEE
#define BK1_EF_Q1H_SETTING 0xEF
// Whatch Dog
#define BK1_F0_WDT0 0xF0
#define WDT_EN_B _BIT5 // Watch Dog Timer Enable
#define WDT_LD_B _BIT6 // Watch Dog Timer Load Value by SW
#define WDT_TESTMD_B _BIT7 // CSOG test mode for WDT counter
#define BK1_F1_WDT1 0xF1 // Watch Dog Timer Width
#define BK1_F2_WRLOCK0 0xF2
#define WRLOCK0_B _BIT7 // 1:Register lock
// pwm control
#define BK1_F3_PWMCLK 0xF3
#define PCLK_B _BIT0 // PWM1/2 base Clock select 1:14.318MHz/4
#define EP1EN_B _BIT1 // Enhance PWM1 Enable
#define P1POL_B _BIT2 // PWM1 Polarity when enhance PWM1 enable
#define EP2EN_B _BIT3 // Enhance PWM2 Enable
#define P2POL_B _BIT4 // PWM2 Polarity when enhance PWM2 enable
#define P1REN_B _BIT5 // PWM1 Reset every frame enable
#define P2REN_B _BIT6 // PWM2 Reset every frame enable
#define DB_EN_B _BIT7 // Double Buffer enable
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