📄 ms7x_reg.h
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#define SL_HS_REMVOE_B _BIT3 // Short line hs remove
#define BK0_87_DEBUG 0x87
#define PTEN_B _BIT3 // PLL test register protect bit
#define BP_B _BIT4
#define ECOK_B _BIT6 // Select external odclk
#define BK0_88_SL_CNTRL_1 0x88
#define FREEZE_SHORTLINE_B _BIT0 // Stop Short Line Update
#define SHORTLINE_FIELD_B _BIT1 // Select short line field
#define INTERLX_CAP_EN_B _BIT2 // Interlance capture enable
#define LIM_HS_B _BIT5 // Limit hs period enable
#define BK0_89_SL_TUNE_1 0x89
#define LOCK_THRESHOLD_Mask 0x1F // [4:0]:Lock_threshold
#define TUNE_COEF_Mask 0xE0 // [7:5]:Tune_coef
#define BK0_8A_SL_TUNE_2 0x8A // Limit_d5d6d7_H:Limit PLL_SET high byte
#define BK0_8B_SL_TUNE_3 0x8B // Limit_d5d6d7_L:Limit PLL_SET low byte
#define BK0_8C_TARGET_SL_L 0x8C // TARGET_SL[7:0]
#define BK0_8D_TARGET_SL_H 0x8D // TARGET_SL[11:8] at [3:0]
#define BK0_8E_REM_L 0x8E
#define BK0_8F_REM_H 0x8F
// Gamma I/O access
#define BK0_90_GAMMA_EN 0x90
#define GAMMA_EN_B _BIT0 // Gamma enable
#define ADR_INC_EN_B _BIT1 // Address increase enable
#define BK0_91_GAMMA_ADR_PORT 0x91
#define BK0_92_GAMMA_DAT_PORT 0x92
//
#define BK0_93_RBIAS 0x93
#define BK0_94_RRATIO 0x94
#define BK0_95_GBIAS 0x95
#define BK0_96_GRATIO 0x96
#define BK0_97_BBIAS 0x97
#define BK0_98_BRATIO 0x98
#define BK0_99_RBIASN 0x99
#define BK0_9A_RRATION 0x9A
#define BK0_9B_GBIASN 0x9B
#define BK0_9C_GRATION 0x9C
#define BK0_9D_BBIASN 0x9D
#define BK0_9E_BRATION 0x9E
#define BK0_9F 0x9F
// OSD I/O access
#define BK0_A0_OSDIOA 0xA0
#define ORBR_B _BIT0 // Enable OSD Register Burst Read Mode
#define ORBW_B _BIT1 // Enable OSD Register Burst Write Mode
#define DA_B _BIT2 // Enable OSD Display Attribute I/O Access
#define DC_B _BIT3 // Enable OSD Display Code I/O Access
#define RF_B _BIT4 // Enable OSD RAM Font I/O Access
#define CLR_B _BIT6 // OSD clear bit
#define TOSBM_B _BIT7 // Enable OSD SRAM I/O Access Burst Mode
#define BK0_A1_OSDRA 0xA1 // [5:0]:OSD Register Address Port
#define BK0_A2_OSDRD 0xA2 // OSD Register Data Port
#define BK0_A3_RAMFA 0xA3 // OSD Ram Font Address Port
#define BK0_A4_RAMFD 0xA4 // OSD Ram Font Data Port
#define BK0_A5_DISPCA_L 0xA5 // OSD Display code Address Port
#define BK0_A6_DISPCA_H 0xA6 // [2:0]: OSD Display code Address Port [10:8]
#define BK0_A7_DISPCD 0xA7 // OSD Display code Data Port
#define BK0_A8_DISPAA_L 0xA8 // OSD display Attribute Address Port
#define BK0_A9_DISPAA_H 0xA9 // [2:0]:OSD display Attribute Address Port [10:8]
#define BK0_AA_DISPAD 0xAA // OSD display Attribute Data Port
#define BK0_AB 0xAB
#define BK0_AC 0xAC
#define BK0_AD 0xAD
#define BK0_AE 0xAE
#define BK0_AF 0xAF
//
#define BK0_B0_LINE_SHIFT 0xB0
#define LINE_SHIFT_NUM_Mask 0x07 // [2:0]:line shift numbers
#define FIELD_INV_VS_B _BIT3 // line shift vs field inverse
#define BK0_B1_SYNC_CONTROL 0xB1
#define HS_INV_B _BIT0 // Ohs inverse
#define VS_INV_B _BIT1 // Ovs inverse
#define DE_INV_B _BIT2 // Ode inverse
#define CLK_INV_B _BIT3 // Odclk inverse
#define CLK_DLY_SEL_Mask 0xF0 // [7:4]:Select odclk delay
#define BK0_B2_SYNC_SEL 0xB2
#define DATA_SKEW_Mask 0x03 // [1:0]:Bus data skew select
#define SEL_HDE_B _BIT2 // Select hde output to hs pin
#define SEL_VDE_B _BIT3 // Select vde output to vs pin
#define BK0_B3_SVM_CLK 0xB3
#define SVM_CLKDLY_Mask 0x0F // [3:0]:Svm clock delay select
#define SVM_CLK_INV_B _BIT4 // Svm clock inverse
#define BK0_B4 0xB4
#define BK0_B5 0xB5
#define BK0_B6 0xB6
#define BK0_B7 0xB7
#define BK0_B8 0xB8
#define BK0_B9 0xB9
#define BK0_BA 0xBA
#define BK0_BB 0xBB
#define BK0_BC 0xBC
#define BK0_BD 0xBD
#define BK0_BE 0xBE
#define BK0_BF 0xBF
#define BK0_C0 0xC0
#define BK0_C1 0xC1
#define BK0_C2 0xC2
#define BK0_C3 0xC3
#define BK0_C4 0xC4
#define BK0_C5 0xC5
#define BK0_C6 0xC6
#define BK0_C7 0xC7
#define BK0_C8_ATGCTRL 0xC8
#define ATGE_B _BIT0 // Auto Gain Function Enable
#define ATGR_B _BIT1 // Auto Gain Result Ready(RO)
#define ATGM_B _BIT2 // Auto Gain Mode
#define AGR_B _BIT3 // Auto Gain Result slecction
#define ACE_B _BIT4 // ADC Calibration Enable
#define MAXB_B _BIT5 // Max value flag for blue channel(RO)
#define MAXG_B _BIT6 // Max value flag for green channel(RO)
#define MAXR_B _BIT7 // Max value flag for red channel(RO)
#define BK0_C9_ATGST 0xC9
#define MINB_B _BIT0 // Min value flag for blue channel(RO)
#define MING_B _BIT1 // Min value flag for green channel(RO)
#define MINR_B _BIT2 // Min value flag for red channel(RO)
#define CALB_B _BIT3 // Calibration value flag for Blue channel(RO)
#define CALG_B _BIT4 // Calibration value flag for Green channel(RO)
#define CALR_B _BIT5 // Calibration value flag for Red channel(RO)
#define VCLP_B _BIT7 // Video auto gain mode 0/1:RGB/YPbPr mode
#define BK0_CA_ATFCHSEL 0xCA
// [2:0] Auto Gain R/G/B channel min/max value select
// [5:4] Auto Phase R/G/B channel select
#define MIN_R 0x00
#define MIN_G 0x01
#define MIN_B 0x02
#define MAX_R 0x03
#define MAX_G 0x04
#define MAX_B 0x05
#define BK0_CB_ATOCTRL 0xCB
#define ATOE_B _BIT0 // Auto position function enable
#define ATOR_B _BIT1 // Auto position result Ready(RO)
#define ATOM_B _BIT2 // Auto position function mode
#define JITR_B _BIT3 // Jitter function Result(RO)
#define JITM_B _BIT4 // Jitter function Mode
#define JITS_B _BIT6 // Jitter Software clear
#define JITLR_B _BIT7 // Jitter function (0/1)Left/Right result for D6h and D7h
#define BK0_CC_AOVDV 0xCC
// [7:4] Auto position Valid Data Value
#define BK0_CD_ATGVALUE 0xCD // Auto Gain result based on CAh[2:0](RO)
#define BK0_CE_AOVST_L 0xCE // Auto position detected result Vertical Starting point(RO)
#define BK0_CF_AOVST_H 0xCF // [2:0]:AOVST[10:8](RO)
#define BK0_D0_AOHST_L 0xD0 // Auto position detected result Horizontal Starting point(RO)
#define BK0_D1_AOHST_H 0xD1 // [2:0]:AOHST[10:8](RO)
#define BK0_D2_AOVEND_L 0xD2 // Auto position detected result Vertical End point(RO)
#define BK0_D3_AOVEND_H 0xD3 // [2:0]:AOVEND[10:8](RO)
#define BK0_D4_AOHEND_L 0xD4 // Auto position detected result Horizontal End point(RO)
#define BK0_D5_AOHEND_H 0xD5 // [2:0]:AOHEND[10:8](RO)
#define BK0_D6_JLR_L 0xD6 // Jitter function detected Left/Right most point state(RO)
#define BK0_D7_JLR_H 0xD7 // [2:0]:JLR[10:8](RO)
#define BK0_D8_ANRF 0xD8
// [2:0] Auto Noise Level
#define BGEN_B _BIT4 // Background Noise reduction Enable
#define HNEN_B _BIT5 // High level Noise reduction Enable
#define BK0_D9_ATPGTH 0xD9 // Auto Phase Gray scale Threshold for ATPV3 when ATPV4=0
#define BK0_DA_ATPTTH 0xDA // Auto Phase Text Threshold for ATPV4
#define BK0_DB_ATPCTRL 0xDB
#define ATPE_B _BIT0 // Auto Phase function Enable
#define ATPR_B _BIT1 // Auto Phase Result Ready(RO)
#define APMASK_Mask 0x1C // Noise Mask
#define TXT_B _BIT5 // Text detect(RO)
#define GRY_B _BIT6 // Gray scale detect(RO)
#define ATP_ELTRMD_B _BIT7 // Enable auto-position filter mode
#define BK0_DC_ATPV1 0xDC // Auto Phase Value(RO) ATPVALUE[7:0]
#define BK0_DD_ATPV2 0xDD // [7:0]:ATPVALUE[15:8]
#define BK0_DE_ATPV3 0xDE // [7:0]:ATPVALUE[23:16]
#define BK0_DF_ATPV4 0xDF // [7:0]:ATPVALUE[31:24]
//
#define BK0_E0_PDMD0 0xE0
#define FSCCLK_INV_B _BIT0 // Sub-carrier clock inverting
#define IDCLK_INV_B _BIT1 // Scaler input sample clock inverting
#define EOCLK_INV_B _BIT2 // External OSD sample clock inverting
#define MCUCLKDIV2_B _BIT3 // MCU clock select, 0/1:crystal clock/1/2 crystal clock
#define CMBCLK_GAT_B _BIT4 // Disable MVD comb-filter clock
#define AUXCLK_GAT_B _BIT5 // Disable MVD MCU-support clock
#define GCLK_Mask 0xC0 // [7:6]:Gated Clock for SRAM
#define BK0_E1_PDMD1 0xE1
#define FSCCLK_GAT_B _BIT0 // Disable MVD digital front-end clock
#define IDCLK_GAT_B _BIT1 // Disable scaler clock
#define VDCLK_GAT_B _BIT2 // Disable CCIR and MVD interface clock
#define ADCCLK_GAT_B _BIT3 // Disable 3-channel ADC digital clock
#define PCCLK_GAT_B _BIT4 // Disable CRT output support clock
#define OSDCLK_GAT_B _BIT5 // Disable OSD clock
#define BIUCLK_GAT_B _BIT6 // Disable register interface clock
#define PDALL_B _BIT7 // All chip power down
#define BK0_E2_SWRST0 0xE2
#define SWR_B _BIT0 // Software Reset (reset all digital core except registers)
#define OSDR_B _BIT1 // Reset internal OSD
#define OP2R_B _BIT3 // Reset Display Port
#define OP1R_B _BIT4 // Reset Scaler
#define IPR_B _BIT5 // Reset Digital Input Port
#define ADCR_B _BIT6 // Reset ADC
#define REGR_B _BIT7 // Reset Register
#define BK0_E3_SWRST1 0xE3
#define GMCR_B _BIT4 // Reset GMC digital tune
#define MCUR_B _BIT5 // Reset Embedded MCU
#define VCFR_B _BIT6 // Reset Video Decoder Comb Filter
#define VFER_B _BIT7 // Reset Video Decoder Front End
#define BK0_E4_ISOVRD 0xE4
#define INTJ_B _BIT0 // Interlace judgment
#define UINT_B _BIT1 // User defined 0/1:Non-interlace/Interlace, active when INTJ=1
#define IHSJ_B _BIT2 // Input HSYNC polarity judgment; 1:Defined by user (UHSP)
#define UHSP_B _BIT3 // User defined inpt HSYNC Polarity; 0/1:Low/High
#define IVSJ_B _BIT4 // Input VSYNC polarity judgment; 1:Defined by user (UVSP)
#define UVSP_B _BIT5 // User defined inpt VSYNC Polarity; 0/1:Low/High
#define CSHS_B _BIT6 // HSYNC in coast; 0/1:HSYOUT/Re-shaped HSYNC
#define SL_B _BIT7 // Shift Line; 0/1:Method 0/Method 1 for interlace mode
#define BK0_E5_MDCTRL 0xE5
#define IFI_B _BIT0 // Interlace Field inverting
#define INTF_SEL_B _BIT1 // Interlace Field detect method select
#define VEXF_B _BIT2 // Use Video External Field
#define VFIV_B _BIT3 // Video Filed Inversion
#define FIELD_ABSMD_B _BIT4 // Field Position Absolute Value Mode
#define VERR_B _BIT5 // Video CCIR656 Error correct
#define IP_TEST_MD_Mask 0xC0 // [7:6]:IP test-bus selection
#define BK0_E6_HSPW 0xE6 // HS Pulse width(RO)
#define BK0_E7_VFREE 0xE7
#define MIN_VTT_Mask 0x3F // [5:0]:Minimum VTT to free run
#define AUTOOPCOAST_B _BIT6 // Enable auto-coast-for-output
#define AUTOOPCOAST_CLR_B _BIT7 // Set auto-coast-for-output status
#define BK0_E8_HSTOL 0xE8
#define HSTOL_Mask 0x3F // [5:0]:HSYNC Tolerance
#define LN4_DETMD_B _BIT6 // 4 Line Detect Mode for Hs, DE
#define VS2HS_B _BIT7 // Input VSYNC too close to input HSYNC(RO)
#define BK0_E9_VSTOL 0xE9
#define VSTOL_Mask 0x0F // [3:0]:VSYNC Tolerance
#define HVTT_LOSE_MD_B _BIT4 // HVtt lose mode
#define HTT_FILTERMD_B _BIT5 // Htt Filter Mode
#define AUTONOSIGNAL_B _BIT6 // Enable auto-no-signal function
#define AUTONOSIGNAL_CLR_B _BIT7 // Set auto-no-signal status
#define BK0_EA_HSPRD_L 0xEA // Input Horizontal Period, count by reference clock [7:0](RO)
#define BK0_EB_HSPRD_H 0xEB // HSPRD[12:8] at [4:0](RO)
#define BK0_EC_VTOTAL_L 0xEC // Input Vertical Total Lenght, count by HSYNC [7:0](RO)
#define BK0_ED_VTOTAL_H 0xED // VTOTAL[10:8] at [2:0](RO)
#define BK0_EE_PDMD2 0xEE // MCU clock source select
#define BK0_EF_STATUS2 0xEF //(RO)
#define IVSP_B _BIT0 // Incoming input VSYNC polarity detecting result by this chip
#define IHSP_B _BIT1 // Incoming input HSYNC polarity detecting result by this chip
#define INTF_B _BIT2 // Input odd/Even:1/0 field detecting result by this chip
#define INTM_B _BIT3 // Interlace/Non-interlace:1/0 detecting result by this chip
#define CSD_B _BIT4 // CSYNC Detected status; 1:Input is detected as CSYNC
#define STD_PAL_B _BIT5 // 0/1:NTSC/PAL
#define HTT_CHG_CS_B _BIT7 // Htotal change in CSOG
// Chip ID and Version
#define BK0_F0_CHIP_ID 0xF0 // Chip id is 70h
#define BK0_F1_CHIP_VERSION 0xF1 // Chip version is 00h
#define BK0_F2 0xF2
#define BK0_F3 0xF3
#define BK0_F4_TRISTATE 0xF4
#define CLK_TRI_B _BIT0 // Output clk tristate
#define DE_TRI_B _BIT1 // Output de tristate
#define HS_TRI_B _BIT2 // Output hs tristate
#define VS_TRI_B _BIT3 // Output vs tristate
#define OBUS_TRI_B _BIT4 // Output bus tristate
#define BK0_F5 0xF5
#define BK0_F6 0xF6
// Test function control registers
#define BK0_F7_TEST_BUS_SELECT 0xF7
#define BK0_F8_TEST_MODE 0xF8
#define BK0_F9_BIST_RESULT 0xF9
#define BK0_FA_BIST_RESULT_L 0xFA
#define BK0_FB_BIST_RESULT_H 0xFB
#define BK0_FC 0xFC
#define BK0_FD 0xFD
#define BK0_FE_BOUNDING_INF 0xFE
#define BK0_FF_BOUNDING_MISC 0xFF
//=====================================================================
// Bank = 01 (ACE Register)
#define BK1_01_DBFC 0x01 // enable dobule buffer while vertical blanking
#define BK1_02_PLLDIVM 0x02 // PLL divider (HTotal)
#define BK1_03_PLLDIVL 0x03
#define BK1_04_RGAIN_ADC 0x04 // ADC R gain
#define BK1_05_GGAIN_ADC 0x05 // ADC G gain
#define BK1_06_BGAIN_ADC 0x06 // ADC B gain
#define BK1_07_ROFFS_ADC 0x07 // ADC R offset
#define BK1_08_GOFFS_ADC 0x08 // ADC G offset
#define BK1_09_BOFFS_ADC 0x09 // ADC B offset
#define BK1_0A_CLPACE 0x0A // Clamp Placement based on ADC clock
#define BK1_0B_CLDUR 0x0B // Clamp Duration based on ADC clock
#define BK1_0C_GCTRL 0x0C
#define BK1_0D_BWCOEF 0x0D // PLL loop filter control
#define BK1_0E_FCOEF 0x0E // PLL loop filter control
#define BK1_0F_DCOEF 0x0F // PLL loop filter control
//Clock Phase control
#define BK1_10_CLKCTRL1 0x10 // Clock Phase adjust
#define BK1_11_CLKCTRL2 0x11 // Clock Phase adjust
#define BK1_12_VCOCTRL 0x12
#define BK1_13_RT_CT 0x13
#define BK1_14_SOG_LVL 0x14
#define BK1_15 0x15
#define BK1_16_DITHCTRL 0x16
#define BK1_17_CLAMP_CTRL 0x17
#define BK1_18_CALEN 0x18
#define BK1_19_CALCTL 0x19
#define BK1_1A_CALSMP 0x1A
#define BK1_1B_CALDUR 0x1B
#define BK1_1C_CALDLY 0x1C
#define BK1_1D_STATUS_CAL 0x1D
#define BK1_1E_STATUS_PLL 0x1E
#define BK1_1F_ADC_ICTRL 0x1F
#define BK1_20_TESTD0 0x20
#define BK1_21_TESTD1 0x21
#define BK1_22_TESTD2 0x22
#define BK1_23_FPLL_STATUS 0x23
#define BK1_24_FPLL_MD 0x24
#define BK1_25_FPLL_DIVN 0x25
#define BK1_26_FPLL_TEST_H 0x26
#define BK1_27_FPLL_TEST_M 0x27
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