📄 mst7x.lst
字号:
479
480 2, BK4_7A,
481 0xFF, 0x38,
482 1,BK4_81,
C51 COMPILER V7.50 MST7X 03/18/2008 22:29:09 PAGE 9
483 0x90,
484 1, BK4_86,
485 0x01,
486
487 1, BK4_85,
488 0x3C,
489
490 1, BK4_8A,
491 0x01,
492
493 1,BK4_89,
494 0x16,
495
496 #if CCFL_BURST_MODE
497 1, BK4_8F,
498 0x00,
499
500 1, BK4_8E,
501 0xAE,
502 #endif
503
504 1,BK4_91,
505 0x00,
506
507 1,BK4_90,
508 0x80,
509
510 2,BK4_AB,
511 0x13, 0x81,
512
513 1, BK4_B0,
514 0xB3,
515
516 2, BK4_B1,
517 0x00, 0x0A,
518
519 1, BK4_6B,
520 0x00,
521 #endif
522
523 #if PANEL_LVDS
1, BK4_19_LVDS_CTRL, 0x00 // BK4_19_LVDS_CTRL
#if PANEL_LVDS_TI_MODE
|_BIT0
#endif
#if PANEL_SWAP_LVDS_POL
| _BIT1
#endif
#if PANEL_SWAP_LVDS_CH
| _BIT2
#endif
,
1, BK4_1E_MOD_CTRL,
0x02,
2, BK4_20_MOD_SEL0,
0x00, 0x00,
#if (PANEL_TYPE_SEL == PNL_FUJITSU17_L)
1, BK4_22_LVDS_T0,
0x26,
C51 COMPILER V7.50 MST7X 03/18/2008 22:29:09 PAGE 10
#else
1, BK4_22_LVDS_T0,
0x00,
#endif
#elif PANEL_ANALOG_TCON
551
552 1, BK4_1E_MOD_CTRL,
553 0x04,
554
555 #endif
556
557 #endif
558
559 // select register bank scaler (BANK0)
560 //===============================================================
561 1, GEN_00_REGBK,
562 REGBANKSCALER,
563
564 -1,
565
566 };
567
568 #if (PANEL_TCON+PANEL_ANALOG_TCON)
569 BYTE code tPanel_TCONInitial[]=
570 {
571 1, GEN_00_REGBK, // select register bank ADC
572 REGBANKADC,
573
574 3, BK1_CD_GPO_OEV2_WIDTH,
575 SET_OEV2_WIDTH, // BK1_CD_GPO_OEV2_WIDTH
576 SET_OEV3_WIDTH, // BK1_CE_GPO_OEV3_WIDTH
577 SET_OEV_DELTA, // BK1_CF_GPO_OEV_DELTA
578
579 3, BK1_D0_PTC_MODE1,
580 (SET_PTC_MODE1&0x7F), // Initial disable TCON // BK1_D0_PTC_MODE1
581 #if ((BOARD_TYPE_SEL == BD_DEMO_7985M_IDP)||(BOARD_TYPE_SEL == BD_SOCKET_7985M_IDP)||(BOARD_TYPE_SEL == BD
-_SOCKET_7915MA_IDP)) // BK1_D1_PTC_MODE2
(SET_PTC_MODE2&0xFC|0x01), // Initial set R/L output low and U/D output High for Panel VDD
#else
584 (SET_PTC_MODE2&0xFC), // Initial set R/L and U/D output low
585 #endif
586 SET_PTC_MODE3, // BK1_D2_PTC_MODE3
587
588 20, BK1_DC_GPO_FRP_TRAN,
589 SET_FRP_TRAN, // BK1_DC_GPO_FRP_TRAN
590 SET_STH_START, // BK1_DD_GPO_STH_STT
591 SET_STH_WIDTH, // BK1_DE_GPO_STH_WIDTH
592 SET_OEH_START, // BK1_DF_GPO_OEH_STT
593 SET_OEH_WIDTH, // BK1_E0_GPO_OEH_WIDTH
594 SET_OEV_START, // BK1_E1_GPO_OEV_STT
595 SET_OEV_WIDTH, // BK1_E2_GPO_OEV_WIDTH
596 SET_CKV_START, // BK1_E3_GPO_CKV_STT
597 SET_CKV_START2, // BK1_E4_GPO_CKV_STT2
598 SET_CKV_WIDTH, // BK1_E5_GPO_CKV_WIDTH
599 SET_STV_LINE_TH, // BK1_E6_GPO_STV_LN_TH
600 SET_STV_START, // BK1_E7_GPO_STV_STT
601 SET_STV_WIDTH, // BK1_E8_GPO_STV_WIDTH
602 SET_OEV2_START, // BK1_E9_GPO_OEV2_STT
603 SET_OEV3_START, // BK1_EA_GPO_OEV3_STT
604 SET_H_ST_DLY_L, // BK1_EB_HSTT_DLY_L
605 SET_H_ST_DLY_H, // BK1_EC_HSTT_DLY_H
C51 COMPILER V7.50 MST7X 03/18/2008 22:29:09 PAGE 11
606 SET_CLK_DLY_SYNC_OUT, // BK1_ED_CLK_DLY_SYNC_OUT
607 SET_CKV_END2, // BK1_EE_GPO_CKV_END2
608 SET_Q1H, // BK1_EF_Q1H_SETTING
609
610 #if PANEL_ANALOG_TCON
611
612 2, BK1_43_BVOM_DC, // VCOM setting
613 SET_BVOM_DC, // BK1_43_BVOM_DC
614 SET_BVOM_OUT, // BK1_44_BVOM_OUT
615
616 10, BK1_46, // Power setting
617 0x00, 0x00, 0x00, 0x0C, // BK1_46, BK1_47_C_BUCK, BK1_48_C_CP, BK1_49 // 20050701 update
618 0x00, 0x40, 0x55, 0x55, // BK1_4A, BK1_4B, BK1_4C, BK1_4D
619 0xF9, 0x00, // BK1_4E, BK1_4F
620
621 2, BK1_AA_VDAC_ADJ1, // DAC output setting
622 SET_VDAC_ADJ1, // BK1_AA_VDAC_ADJ1
623 SET_VDAC_ADJ2, // BK1_AB_VDAC_ADJ2
624
625 #else
2, BK1_45,
0x01, 0x50, // BK1_45,BK1_46
3, BK1_4A,
0xF1, 0x5F, 0x55, // BK1_4A, BK1_4B, BK1_4C
1, BK1_A9_PD_VDAC,
0x0F, // BK1_A9_PD_VDAC
#endif // PANEL_ANALOG_TCON
636
637 1, GEN_00_REGBK, // select register bank scaler
638 REGBANKSCALER,
639
640 -1,
641
642 };
643 #endif //(PANEL_TCON+PANEL_ANALOG_TCON)
644
645 /**********************
646 * FUNCTION PROTOTYPES *
647 ***********************/
648 void mstMst7XInit(void)
649 {
650 1 mstPowerManagement(PM_POWER_ON); // Enable all of CLK
651 1
652 1 mstWriteByte(GEN_00_REGBK, REGBANKSCALER); // select register bank scaler
653 1 mstWriteByte(BK0_E2_SWRST0, 0x01); // software reset
654 1 miscDelay1ms(1);
655 1 mstWriteByte(BK0_E2_SWRST0, 0x00); // software reset
656 1 miscDelay1ms(20);
657 1
658 1 // Mst7xxx initial
659 1 mstWriteDataTable(tMST7xInitialize);
660 1
661 1 // msACE libary initial
662 1 InitACEVar();
663 1 tColorCorrectionMatrix = &(tVideoColorCorrectionMatrix[0][0]);
664 1 //msACEColorCtrl(1);
665 1 msAdjustPCRGB(0x80, 0x80, 0x80);
666 1 msAdjustVideoRGB(0x80, 0x82, 0x80);
667 1 msAdjustHSC(50, 0x80, 0x80);
C51 COMPILER V7.50 MST7X 03/18/2008 22:29:09 PAGE 12
668 1 msAdjustVideoCbCr(_COLOR_DEF_CB,_COLOR_DEF_CR);
669 1
670 1 // Panel timing initial
671 1 mstWriteDataTable(tPanel_InitialTable);
672 1
673 1 // Load ACE initial table
674 1 mstWriteDataTable(tMsACETable);
675 1 #if (MARIA_TYPE_SEL == MARIA_1)
mstWriteByte(GEN_00_REGBK, REGBANKADC); // Switch bank1 ADC
g_ucMBRIValue = mstReadByte(BK1_85_M_BRI);
mstWriteByte(GEN_00_REGBK, REGBANKSCALER); // Switch bank0 Scaler
#endif
680 1
681 1 #if (PANEL_TCON+PANEL_ANALOG_TCON)
682 1 mstWriteDataTable(tPanel_TCONInitial);
683 1 #else // (PANEL_TCON+PANEL_ANALOG_TCON)
mstWriteByte(GEN_00_REGBK, REGBANKADC); // Switch bank1 ADC
mstWriteByte(BK1_D0_PTC_MODE1, 0x0C); // Disable TCON function
mstWriteByte(GEN_00_REGBK, REGBANKSCALER); // Switch bank0 Scaler
#endif // (PANEL_TCON+PANEL_ANALOG_TCON)
688 1
689 1 #if SSC_ENABLE
690 1 mstEnableSSC();
691 1 #endif
692 1
693 1 #if(MARIA_TYPE_SEL == MARIA_2)
694 1 mstWriteByte( BK0_24_OPL_CTL1, 0x03);
695 1 mstWriteByte( BK0_2D_OPL_TSTA0, 0x00);
696 1 #if (PANEL_LVDS)
mstWriteByte( BK0_2E_OPL_TSTA1, 0x00);
#else
699 1 mstWriteByte( BK0_2E_OPL_TSTA1, 0x05);
700 1 #endif
701 1 #endif
702 1 // Initialize OSD
703 1 //osdOsdInitial(); //20050908 kevin mask
704 1 }
705
706
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = 142 ----
CONSTANT SIZE = 683 ----
XDATA SIZE = ---- ----
PDATA SIZE = ---- ----
DATA SIZE = ---- ----
IDATA SIZE = ---- ----
BIT SIZE = ---- ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -