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📄 mst7x.lst

📁 MST720-DEMO程序
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C51 COMPILER V7.50   MST7X                                                                 03/18/2008 22:29:09 PAGE 1   


C51 COMPILER V7.50, COMPILATION OF MODULE MST7X
OBJECT MODULE PLACED IN ..\1out\Mst7x.obj
COMPILER INVOKED BY: D:\设计软件\Keil\C51\BIN\C51.EXE ..\SCALER\Mst7x.c BROWSE INCDIR(..\INC\;..\PANEL\;..\UI\;..\OPTION
                    -\;..\SCALER\DSP\) DEFINE(MCU_TYPE_SEL=0) DEBUG OBJECTEXTEND PRINT(..\1out\Mst7x.lst) OBJECT(..\1out\Mst7x.obj)

line level    source

   1          /******************************************************************************
   2           Copyright (c) 2005 MStar Semiconductor, Inc.
   3           All rights reserved.
   4          
   5           [Module Name]: Mst7xxx.c
   6           [Date]:        17-Jan-2005
   7           [Comment]:
   8             Functions For Mst7xxx IC.
   9           [Reversion History]:
  10          *******************************************************************************/
  11          #define _MST7X_C_
  12          
  13          /********************
  14          * INCLUDE FILES     *
  15          *********************/
  16          #include "Project.h"
  17          #include "Mcu_reg.h"
  18          #include "TypeDef.h"
  19          #include "msACE.h"
  20          #include "Ms_RWreg.h"
  21          #include "Ms7X_reg.h"
  22          #include "Mst7x.h"
  23          #include "Ms_Func.h"
  24          #include "Debug.h"
  25          #include "Misc.h"
  26          #include "PANEL.h"
  27          #include "OSDFunc.h"
  28          #include "Global.h"
  29          
  30          /********************
  31          * STATIC DATA       *
  32          *********************/
  33          BYTE code tMST7xInitialize[]=
  34          {
  35          // select register bank scaler (BANK0)
  36          //===============================================================
  37                  1, GEN_00_REGBK,                                
  38                  REGBANKSCALER,                          // 00h
  39          
  40                  4, BK0_01_DBFC,
  41                  0x00, 0x0C, 0x00, 0x10,                 // BK0_01_DBFC, BK0_02_ISELECT, BK0_03_IPCTRL2, BK0_04_ISCTRL
  42                  
  43          #if PANEL_TYPE_SEL == PNL_AU20_D
                      0x04, BK0_0D_LYL,
                      0x04, 0x00, 0x20, 0x20,                 // BK0_0D_LYL, BK0_0E_INTLX, BK0_0F_ASCTRL, BK0_10_COCTRL1
              #elif ((PANEL_TYPE_SEL == PNL_AU07_AT)||(PANEL_TYPE_SEL == PNL_LG07_AT)||(PANEL_TYPE_SEL == PNL_TMD08_AT)|
             -|(PANEL_TYPE_SEL == PNL_PVI09_AT)||(PANEL_TYPE_SEL == PNL_AU85_AT))//kevin
                      0x04, BK0_0D_LYL,
                      0x04, 0x00, 0x10, 0xA0,                 // BK0_0D_LYL, BK0_0E_INTLX, BK0_0F_ASCTRL, BK0_10_COCTRL1
              #else
  50                  0x04, BK0_0D_LYL,
  51                  0x00, 0x00, 0x10, 0x20,                 // BK0_0D_LYL, BK0_0E_INTLX, BK0_0F_ASCTRL, BK0_10_COCTRL1
  52          #endif
  53          
C51 COMPILER V7.50   MST7X                                                                 03/18/2008 22:29:09 PAGE 2   

  54          #if ((MARIA_TYPE_SEL == MARIA_2) && ENABLE_VD_DSP)
                      1, BK0_0E_INTLX,
                      0x80,
              
                      // 1, BK0_1D_INTENC,
                      // 0x40,
              #endif
  61          
  62                  // Interrupt setting
  63                  0x02, BK0_16_INTCTROL,
  64                  0x00, 0x0F,                             // BK0_16_INTCTROL, BK0_17_INTPULSE
  65                  
  66                  0x01, BK0_1F_INTEND,
  67                  0x40,                                   // BK0_1F_INTEND
  68          
  69                  // MPLL setting 216Mhz
  70                  0x01, BK0_22_MPL_M,
  71                  0x72,                                   // BK0_22_MPL_M
  72          
  73          #if SSC_ENABLE
  74                  #if(MARIA_TYPE_SEL == MARIA_2)
  75                          0x02, BK0_23_OPL_CTL0,
  76                          0x40, 0x03,
  77                          #if(PANEL_TYPE_SEL == PANEL_LVDS)
                                      0x02, BK0_2D_OPL_TSTA0,
                                      0x00, 0x00,
                              #else
  81                                  0x02, BK0_2D_OPL_TSTA0,
  82                                  0x00, 0x05,
  83                          #endif
  84                  #else
                              0x01, BK0_23_OPL_CTL0,
                              0x40,                                   // BK0_23_OPL_CTL0
                      #endif
  88                  
  89                  0x04, BK0_28_OPL_STEP0,                         
  90                  DEF_SSC_STEP0, DEF_SSC_STEP1,           // BK0_28_OPL_STEP0, BK0_29_OPL_STEP1
  91                  DEF_SSC_SPAN0, DEF_SSC_SPAN1,           // BK0_2A_OPL_SPAN0, BK0_2B_OPL_SPAN1
  92                  
  93          #else
                      #if(MARIA_TYPE_SEL == MARIA_2)
                              0x02, BK0_23_OPL_CTL0,
                              0x00, 0x07,
                              #if(PANEL_TYPE_SEL == PANEL_LVDS)
                                      0x02, BK0_2D_OPL_TSTA0,
                                      0x00, 0x00,
                              #else
                                      0x02, BK0_2D_OPL_TSTA0,
                                      0x00, 0x05,
                              #endif
                      #else
                              0x01, BK0_23_OPL_CTL0,
                              0x00,                                   // BK0_23_OPL_CTL0
                      #endif
              #endif
 109          
 110                  0x01, BK0_57_OSCTRL1,
 111                  0x42,                                   // BK0_57_OSCTRL1
 112          
 113                  0x02, BK0_5C_FRAME_COLOR_1,             // Set frame color and enable
 114                  0x3F, 0x00,                             // BK0_5C_FRAME_COLOR_1, BK0_5D_FRAME_COLOR_2
 115          
C51 COMPILER V7.50   MST7X                                                                 03/18/2008 22:29:09 PAGE 3   

 116                  0x12, BK0_64_CM11_L,                    // 3X3 color matrix
 117                  0x3B, 0x06, 0x18, 0x05, 0x00, 0x00,             // BK0_64, BK0_65, BK0_66, BK0_67, BK0_68, BK0_69
 118                  0x2C, 0x13, 0x18, 0x05, 0x87, 0x11,             // BK0_6A, BK0_6B, BK0_6C, BK0_6D, BK0_6E, BK0_6F
 119                  0x00, 0x00, 0x18, 0x05, 0xE1, 0x07,             // BK0_70, BK0_71, BK0_7h, BK0_73, BK0_74, BK0_75
 120          
 121          #if ((BOARD_TYPE_SEL == BD_DEMO_7985M_IDP)||(BOARD_TYPE_SEL == BD_SOCKET_7985M_IDP)||(BOARD_TYPE_SEL == BD
             -_SOCKET_7915MA_IDP))
                      1, BK0_87_DEBUG,                                // Select PWM1/2 output 
                      0x0A,                                   // BK0_87_DEBUG
              #else
 125                  1, BK0_87_DEBUG,                                // Select PWM1/2 output 
 126                  0x08,                                   // BK0_87_DEBUG
 127          #endif
 128          
 129                  2, BK0_CB_ATOCTRL,
 130                  0x01, 0x40,                             // BK0_CB_ATOCTRL, BK0_CC_AOVDV
 131                  
 132                  2, BK0_E4_ISOVRD,
 133                  0x00, 0x00,                             // BK0_E4_ISOVRD, BK0_E5_MDCTRL
 134          
 135                  0x02, BK0_E8_HSTOL,                     // Set Hsync and Vsync tolerance
 136                  0x05, 0x01,                             // BK0_E8_HSTOL, BK0_E9_VSTOL
 137          
 138          #if(MARIA_TYPE_SEL == MARIA_2)
 139                  0x01, BK0_F7_TEST_BUS_SELECT,
 140                  0x08,
 141          #endif
 142                                  
 143                  0x01, BK0_F8_TEST_MODE,                 // Disable test mode
 144                  0x00,                                   // BK0_F8_TEST_MODE
 145          
 146          // select register bank adc (BANK1)
 147          //===============================================================
 148                  1, GEN_00_REGBK,                                
 149                  REGBANKADC,                             // 00h
 150          
 151                  1, BK1_0C_GCTRL,                                // For YPbPr and VGA Hync input polarity
 152                  0x02,                                   // BK1_0C_GCTRL
 153          
 154          #if FSC_8X
 155                  1, BK1_16_DITHCTRL,
 156                  0x70,                                   // BK1_16_DITHCTRL
 157          #endif  // FSC_8X
 158          
 159                  1, BK1_2C_RGB_BW_SEL1,                  // iClamp (20050614 update)
 160                  0xF0,                                   // BK1_2C_RGB_BW_SEL1
 161          
 162                  1, BK1_33,                              // SOG filter bandwidth
 163                  0x18,                                   // BK1_33
 164          
 165                  1, BK1_35,                              // for SOG threshold (recommend value) 
 166                  0x08,                                   // BK1_35
 167          
 168                  1, BK1_3E,                              // ??
 169                  0x82,                                   // BK1_3E
 170          
 171                  1, BK1_49,
 172                  0x0C,                                   // BK1_49  0x0F   // Forte0714 ON/OFF BUCK current sense.
 173          
 174                  1, BK1_4E,
 175                  0xF9,                                   // BK1_4E  0x59   // Forte0714 increase reference current for BUCK current sense.
 176          
C51 COMPILER V7.50   MST7X                                                                 03/18/2008 22:29:09 PAGE 4   

 177                  10, BK1_90_SARADC_CTRL,                 // SAR Key setting
 178                  0x20, 0x20, 0x07, 0x00,         //0X07-0X00     // BK1_90_SARADC_CTRL, BK1_91_SARADC_SAMPRD, BK1_92_SARADC_AISEL, BK
             -1_93_SARADC_TEST
 179                  0x3F, 0x05, 0x3F, 0x00,                 // BK1_94_SAR_CH1_UPB, BK1_95_SAR_CH1_LOB, BK1_96_SAR_CH2_UPB, BK1_97_SAR_CH2_L
             -OB
 180                  0x3F, 0x00,                             // BK1_98_SAR_CH3_UPB, BK1_99_SAR_CH3_LOB
 181          
 182          #if ((MARIA_TYPE_SEL == MARIA_2) && PANEL_LVDS)
                      1, BK1_AC_EN_CDAC,
                      0x01,
              #endif
 186          
 187          #if ((BOARD_TYPE_SEL == BD_DEMO_7985M_IDP)||(BOARD_TYPE_SEL == BD_SOCKET_7985M_IDP)||(BOARD_TYPE_SEL == BD
             -_SOCKET_7915MA_IDP))
                      1, BK1_F3_PWMCLK,                               // For Backlight control
                      0x18,                                   // BK1_F3_PWMCLK
              #endif
 191          
 192                  1, BK1_F4_PWM1C,
 193                  SET_BACKLIGHT_PWM,                      // BK1_F4_PWM1C
 194          
 195                  2, BK1_F6_PWM1EPL,
 196                  0x00, 0x01,                             // BK1_F6_PWM1EPL, BK1_F7_PWM1EPH
 197          
 198          // select register bank VFE (BANK2)
 199          //===============================================================
 200                  1, GEN_00_REGBK,                        
 201                  REGBANKVFE,                             // 00h
 202          
 203          #if(MARIA_TYPE_SEL == MARIA_2)
 204                  1, BK2_17_FSC_SEL,
 205                  0xF9,
 206          
 207                  1, BK2_19_MVDET_EN,
 208                  0xC2,                                                   // For SECAM input
 209          
 210                  1, BK2_26_APL_K1_NORMAL,
 211                  0x30,
 212                  
 213                  1, BK2_27_APL_K2_NORMAL,                // ?? (20050609)
 214                  0x08,
 215          
 216                  1, BK2_4A_AGC_LOWTH,                    // 20051124 Antony
 217                  0xFF,                                                   // BK2_4A_AGC_LOWTH
 218          
 219                  1, BK2_62,                                              // 20051124 Antony
 220                  0x10,                                                   // BK2_62
 221          
 222                  1, BK2_6A_VCR_DETECT1,                  // 20051115.Eric.Lin: Force VCR mode
 223                  0x51,//0xD1,                                                    // BK2_6A_VCR_DETECT1
 224          
 225                  1, BK2_6F,
 226                  0x81,
 227          
 228                  1, BK2_67_WP_REDO,
 229                  0x07,
 230          
 231                  1, BK2_23_APLL_TRANGE, 
 232                  0x80,
 233                  

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