📄 sync.lst
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430 2 mstWriteByte(BK2_7B_656_HDEW, 0xF5);
431 2 #elif (PANEL_WIDTH > 720)
432 2 mstWriteByte(GEN_00_REGBK, REGBANKVFE); // Switch to Bank2 VFE
433 2 mstWriteByte(BK2_7B_656_HDEW, 0xF5);
434 2 #endif*/
435 2 mstWriteByte(GEN_00_REGBK, REGBANKSCALER); // Switch to Bank0 Scaler
436 2 }
437 1
438 1 #else
#if !DEMODULELATOR_MODE
if((ucSyncStatus & DEMODULATION_MODE1_B) != 0)
mstSyncDemodulationModeSet(1); // Set demodulation to mode 1
else
mstSyncDemodulationModeSet(0); // Set demodulation to mode 0
#endif // !DEMODULELATOR_MODE
if ((ucSyncStatus & PAL_MODE_B) != 0)
{
mstWriteDataTable(tSyncCVBSPALTable);
// PATCH setting add follow next:
mstWriteByte(GEN_00_REGBK, REGBANKVFE); // Switch to Bank2 VFE
mstWriteByte(BK2_4D_BRST_WINDOW2, 0xA9);
mstWriteByte(BK2_69_SRC_CTRL1, 0x82);
mstWriteByte(GEN_00_REGBK, REGBANKSCALER); // Switch to Bank0 Scaler
//20050921 mask for VCR //mstWriteByte(BK0_E5_MDCTRL, 0x05); // 20050812 Antony
}
else
{
mstWriteDataTable(tSyncCVBSNTSCTable); // Load NTSC timing table
#if !DEMODULELATOR_MODE
if((ucSyncStatus & DEMODULATION_MODE1_B) != 0)
{
mstWriteDataTable(tSyncCVBSNTSC443Table); // Load NTSC443 timing table
// PATCH setting add follow next:
}
#endif // !DEMODULELATOR_MODE
// PATCH setting add follow next:
mstWriteByte(GEN_00_REGBK, REGBANKVFE); // Switch to Bank2 VFE
mstWriteByte(BK2_4D_BRST_WINDOW2, 0xA0);
mstWriteByte(BK2_69_SRC_CTRL1, 0x82);
mstWriteByte(GEN_00_REGBK, REGBANKSCALER); // Switch to Bank0 Scaler
//20050921 mask for VCR//mstWriteByte(BK0_E5_MDCTRL, 0x04); // 20050812 Antony
}
mstWriteByte(BK0_36_VDSUSG, (mstReadByte(BK0_36_VDSUSG) | 0x0C)); // 20050812 Antony
#endif
480 1 }
481
482 void mstSyncSVideoModeSet(BYTE ucSyncStatus)
483 {
484 1 #if (MARIA_TYPE_SEL == MARIA_2)
485 1 if(ucSyncStatus & _BIT7)
C51 COMPILER V7.50 SYNC 03/18/2008 22:29:09 PAGE 9
486 1 {
487 2 mstWriteDataTable(tSyncSVideoNTSCTable);
488 2 // PATCH setting add follow next:
489 2 mstWriteByte(GEN_00_REGBK, REGBANKVCF); // Switch to Bank3 VCF
490 2 if((ucSyncStatus & 0x07) == 0x02) // For PAL-M mode
491 2 mstWriteByte(BK3_48_BSTLVL_TH, 0x00);
492 2 else
493 2 mstWriteByte(BK3_48_BSTLVL_TH, 0x20);
494 2
495 2 /*#if (PANEL_WIDTH > 900)
496 2 mstWriteByte(GEN_00_REGBK, REGBANKVFE); // Switch to Bank2 VFE
497 2 mstWriteByte(BK2_7B_656_HDEW, 0xE0);
498 2 #elif (PANEL_WIDTH > 720)
499 2 mstWriteByte(GEN_00_REGBK, REGBANKVFE); // Switch to Bank2 VFE
500 2 mstWriteByte(BK2_7B_656_HDEW, 0xE0);
501 2 #endif*/
502 2 mstWriteByte(GEN_00_REGBK, REGBANKSCALER); // Switch to Bank0 Scaler
503 2 }
504 1 else if(ucSyncStatus & _BIT6)
505 1 {
506 2 mstWriteDataTable(tSyncSVideoPALTable);
507 2 // PATCH setting add follow next:
508 2 mstWriteByte(GEN_00_REGBK, REGBANKVCF); // Switch to Bank3 VCF
509 2 mstWriteByte(BK3_48_BSTLVL_TH, 0x00);
510 2
511 2 /*#if (PANEL_WIDTH > 900)
512 2 mstWriteByte(GEN_00_REGBK, REGBANKVFE); // Switch to Bank2 VFE
513 2 mstWriteByte(BK2_7B_656_HDEW, 0xF5);
514 2 #elif (PANEL_WIDTH > 720)
515 2 mstWriteByte(GEN_00_REGBK, REGBANKVFE); // Switch to Bank2 VFE
516 2 mstWriteByte(BK2_7B_656_HDEW, 0xF5);
517 2 #endif*/
518 2 mstWriteByte(GEN_00_REGBK, REGBANKSCALER); // Switch to Bank0 Scaler
519 2 }
520 1
521 1 #else
#if !DEMODULELATOR_MODE
if((ucSyncStatus & DEMODULATION_MODE1_B) != 0)
mstSyncDemodulationModeSet(1); // Set demodulation to mode 1
else
mstSyncDemodulationModeSet(0); // Set demodulation to mode 0
#endif // !DEMODULELATOR_MODE
if ((ucSyncStatus & PAL_MODE_B) != 0)
{
mstWriteDataTable(tSyncSVideoPALTable);
// PATCH setting add follow next:
mstWriteByte(GEN_00_REGBK, REGBANKVFE); //Switch to Bank2 VFE
mstWriteByte(BK2_4D_BRST_WINDOW2, 0xA9);
mstWriteByte(BK2_69_SRC_CTRL1, 0x83);
#if (DEMODULELATOR_MODE)
mstWriteByte(BK2_2D_VDFD_CTRL3, mstReadByte(BK2_2D_VDFD_CTRL3)|0x02); // For mode 1 Chroma Delay issue
#endif // DEMODULELATOR_MODE
mstWriteByte(GEN_00_REGBK, REGBANKSCALER); //Switch to Bank0 Scaler
//20050921 mask for VCR//mstWriteByte(BK0_E5_MDCTRL, 0x05); // 20050812 Antony
}
else
{
mstWriteDataTable(tSyncSVideoNTSCTable);
C51 COMPILER V7.50 SYNC 03/18/2008 22:29:09 PAGE 10
#if !DEMODULELATOR_MODE
if((ucSyncStatus & DEMODULATION_MODE1_B) != 0)
{
mstWriteDataTable(tSyncSVideoNTSC443Table); // Load NTSC443 timing table
// PATCH setting add follow next:
mstWriteByte(GEN_00_REGBK, REGBANKVFE); //Switch to Bank2 VFE
mstWriteByte(BK2_4D_BRST_WINDOW2, 0xA0);
mstWriteByte(GEN_00_REGBK, REGBANKSCALER); //Switch to Bank0 Scaler
return;
}
#endif // !DEMODULELATOR_MODE
// PATCH setting add follow next:
mstWriteByte(GEN_00_REGBK, REGBANKVFE); //Switch to Bank2 VFE
mstWriteByte(BK2_4D_BRST_WINDOW2, 0xA0);
if ((mstReadByte(BK2_01_STATUS1) & 0x07) == 0x00)
mstWriteByte(BK2_69_SRC_CTRL1, 0x85);
else
mstWriteByte(BK2_69_SRC_CTRL1, 0x87);
#if (DEMODULELATOR_MODE)
mstWriteByte(BK2_2D_VDFD_CTRL3, mstReadByte(BK2_2D_VDFD_CTRL3)|0x02); // For mode 1 Chroma Delay issue
#endif // DEMODULELATOR_MODE
mstWriteByte(GEN_00_REGBK, REGBANKSCALER); //Switch to Bank0 Scaler
//20050921 mask for VCR//mstWriteByte(BK0_E5_MDCTRL, 0x04); // 20050812 Antony
}
mstWriteByte(BK0_36_VDSUSG, (mstReadByte(BK0_36_VDSUSG) | 0x0C)); // 20050812 Antony
#endif
576 1 }
577
578 void mstSyncVGAModeSet(BYTE ucSyncStatus)
579 {
580 1 BYTE ucTemp;
581 1
582 1 mstWriteDataTable(tSyncVGAModeTable);
583 1 ucSyncStatus ^= (VSYNC_NEGATIVE_B+HSYNC_NEGATIVE_B);
584 1
585 1 ucTemp = mstReadByte(BK0_03_IPCTRL2);
586 1 ucTemp &= 0xE7; // Clear BK0.03h[4:3]
587 1 ucTemp |= (ucSyncStatus << 3); // Set BK0.03h[4:3] by input sync polarity
588 1 mstWriteByte(BK0_03_IPCTRL2, ucTemp);
589 1
590 1
591 1 }
592
593
594 void mstSyncYPbPrModeSet(BYTE ucSyncStatus)
595 {
596 1 WORD uwVcount;
597 1
598 1 if((ucSyncStatus & INTERLANCE_MODE_B) == 0)
599 1 {
600 2 uwVcount = mstReadWord(BK0_ED_VTOTAL_H) & 0x7FF;
601 2
602 2 if (uwVcount > 560)
603 2 mstWriteDataTable(tSyncYPbPrPALTable);
604 2 else
605 2 mstWriteDataTable(tSyncYPbPrNTSCTable);
606 2
607 2 }
608 1 else
609 1 {
C51 COMPILER V7.50 SYNC 03/18/2008 22:29:09 PAGE 11
610 2 if ((ucSyncStatus & PAL_MODE_B) != 0)
611 2 mstWriteDataTable(tSyncYCbCrPALTable);
612 2 else
613 2 mstWriteDataTable(tSyncYCbCrNTSCTable);
614 2 }
615 1 }
616
617 void mstSyncCCIRModeSet(BYTE ucSyncStatus)
618 {
619 1 if ((ucSyncStatus & PAL_MODE_B) != 0)
620 1 mstWriteDataTable(tSyncCCIRPALTable);
621 1 else
622 1 mstWriteDataTable(tSyncCCIRNTSCTable);
623 1 }
624
625 void mstSyncCheckSignal(void)
626 {
627 1 #if ((MARIA_TYPE_SEL == MARIA_2) && ENABLE_NEW_SYNC)
628 1 BYTE ucBank;
629 1 BYTE ucTemp_VDStatus;
630 1 BYTE ucTemp0_1E = 0;
631 1
632 1 ucBank = mstReadByte(GEN_00_REGBK);
633 1
634 1 if(tOSDSourcSELSequence[Display.ucSourceSEL] < VGA)
635 1 {
636 2 mstWriteByte(GEN_00_REGBK, REGBANKVCF);
637 2
638 2 ucTemp_VDStatus = mstReadByte(BK3_72_COMB_STSC);
639 2
640 2 if((ucTemp_VDStatus != g_ucVDStatus) && ((g_ucSystemFlag&INPUT_TIMING_CHANGE_FLAG) == 0))
641 2 {
642 3 mstEnableMute();
643 3 g_ucVDStatus = ucTemp_VDStatus;
644 3 g_ucSystemFlag |= INPUT_TIMING_CHANGE_FLAG;
645 3 g_ucSystemFlag &= ~INPUT_SIGNAL_STABLE_FLAG;
646 3 g_ucSyncStableCounter = 0;
647 3
648 3 #if (MARIA_TYPE_SEL == MARIA_2)
649 3 mstResetVedioDecoder();
650 3 #endif
651 3
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