📄 f632reg.h
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/*----------------------------------------*/
/* NT68F632 System Register Declare */
/* Date : 2002/10/08 */
/*----------------------------------------*/
#ifndef _F632REG_H
#define _F632REG_H
//#define SysRegOffset 0xf000
//#include "declare.h"
/* General I/O Port Control Registers */
extern xdata unsigned char PortA;
#define PA0 0x01
#define PA1 0x02
#define PA2 0x04
#define PA3 0x08
#define PA4 0x10
#define PA5 0x20
#define PA6 0x40
#define PA7 0x80
extern xdata unsigned char PortB;
#define PB0 0x01
#define PB1 0x02
#define PB2 0x04
#define PB3 0x08
#define PB4 0x10
#define PB5 0x20
#define PB6 0x40
#define PB7 0x80
extern xdata unsigned char PortC;
#define PC0 0x01
#define PC1 0x02
#define PC2 0x04
#define PC3 0x08
#define PC4 0x10
#define PC5 0x20
#define PC6 0x40
#define PC7 0x80
extern xdata unsigned char PortD;
#define PD0 0x01
#define PD1 0x02
#define PD2 0x04
#define PD3 0x08
#define PD4 0x10
#define PD5 0x20
#define PD6 0x40
extern xdata unsigned char PortE;
#define PE0 0x01
#define PE1 0x02
/* GPIO R/W Direction Control */
extern xdata unsigned char RDPA_REG;
extern xdata unsigned char RDPB_REG;
extern xdata unsigned char RDPC_REG;
extern xdata unsigned char RDPD_REG;
extern xdata unsigned char RDPE_REG;
/* Watch-Dog Timer */
extern xdata unsigned char CLRWDT;
#define clrwdt 0x55
/* A/D Converter */
extern xdata unsigned char ADC_CON; // (-W-) : $00
#define STRT_ADC 0x80 // Start A to D Convert
#define EN_ADC3 0x08 // Enable ADC3
#define EN_ADC2 0x04 // Enable ADC2
#define EN_ADC1 0x02 // Enable ADC1
#define EN_ADC0 0x01 // Enable ADC0
extern xdata unsigned char ADC_REG[4]; // (-R-) : ADC0 Value
#define CMP_ADC 0x80 // (-R-): Complete ADC
/* PWM D/A Converters */
extern xdata unsigned char ENPWM_LB; // (-W-) : Enable PWM01-PWM00
extern xdata unsigned char ENPWM_HB; // (-W-) : Enable PWM09-PWM02
extern xdata unsigned char PWM_REG[10];
/* DDC Port-0 PB4,PB5 */
extern xdata unsigned char DDC_CTRL_0;
#define EN_DDC 0x80
#define WPT_DDC 0x40
#define LEN_256 0x20
#define MODE_DDC2 0x10
#define EN_BACK 0x08
#define INVT_CLK 0x04
#define CLR_PTR 0x02
#define CLR_UPD 0x01
#define UPD_DDC 0x01
extern xdata unsigned char DDC_ADDR_0;
#define VALID_B31 0xe0
#define ADDR_B31 0x0e
/* DDC Port-1 PB6,PB7 */
extern xdata unsigned char DDC_CTRL_1;
extern xdata unsigned char DDC_ADDR_1;
/* Interrupt Sources */
extern xdata unsigned char INT_SRC;
#define INTIIC0_IRQ 0x20
#define INTEXT_IRQ 0x10
#define INTIIC1_IRQ 0x02
#define INTHV_IRQ 0x01
/* External Interrupt */
extern xdata unsigned char INTEXT_FLG;
extern xdata unsigned char INTEXT_EN;
#define INTE1 0x02
#define INTE0 0x01
#define INTE1_EDG 0x20
#define INTE0_EDG 0x10
/* SyncProcessor */
/* Sync Processor Interrupt */
extern xdata unsigned char INTHV_FLG;
extern xdata unsigned char INTHV_EN;
#define INT_H 0x80
#define INT_V 0x40
#define INT_HP 0x04
#define INT_VP 0x02
#define INT_FM 0x01 // 1: Enable Fast Mute
/* Sync Procesor Control Register */
extern xdata unsigned char SYNC_REG;
#define EN_FRUN 0x80 // 1: Enable Free-Run Function
#define AUTO_FLT 0x40 // 1: Enable Auto Filter Function
#define EN_SOG 0x20 // 1: Enable SOG Function
#define EN_CLMP 0x10 // 1: Enable Clamp Function
#define EN_PAT 0x08 // 1: Enable Pattern Function
#define EN_HALF 0x04 // 1: Enable HALF Function
#define HALF_SEL 0x02 // 1: HALF_OUT = HALF_IN/2
#define HALF_POL 0x01
extern xdata unsigned char HVO_REG;
#define EN_HOUT 0x80 // 1: Enable HSYNCO Output Pin
#define EN_VOUT 0x40 // 1: Enable VSYNCO Output Pin
#define EN_HRUN 0x20 // 1: Enable Free-Run Horizontal output control
#define EN_VRUN 0x10 // 1: Enable Free-Run Vertical output control
#define EN_INS 0x08 // 1: Enable Insert pulse control
#define SYNCO_SEL 0x04 // 1: Sync outputs from the internal free running gererator
#define HO_POL 0x02
#define VO_POL 0x01
extern xdata unsigned char HVI_REG;
#define SOG_SYNC 0x00
#define SEP_SYNC 0xc0
#define COM_SYNC 0x80
#define INS_1US 0x20
#define H_LVL 0x08
#define V_LVL 0x04
#define HI_POL 0x02
#define VI_POL 0x01
extern xdata unsigned char HPW_REG;
extern xdata unsigned char HFLT_REG;
extern xdata unsigned char CLMP_REG;
extern xdata unsigned char PAT_LT;
extern xdata unsigned char PAT_RT;
extern xdata unsigned char PAT_UP;
extern xdata unsigned char PAT_DN;
extern xdata unsigned char HVCNT_CTRL;
#define VOV_32768 0x00
#define VOV_65536 0x04
#define VOV_98304 0x08
#define VOV_131072 0x0c
#define HGATE_V 0x00
#define HGATE_16384 0x02
#define HGATE_32768 0x03
extern xdata unsigned char HCNT_LB;
extern xdata unsigned char HCNT_HB;
#define HCNTOV 0x80
extern xdata unsigned char VCNT_LB;
extern xdata unsigned char VCNT_HB;
#define VCNTOV 0x80
/*
SysRegX HCNT _at_ 0xf03b;
SysRegX VCNT _at_ 0xf03d;
*/
extern xdata unsigned char DCNT_LB;
extern xdata unsigned char DCNT_HB;
extern xdata unsigned char LCNT_LB;
extern xdata unsigned char LCNT_HB;
extern xdata unsigned char MUTE_CTRL;
#define UPD_HT 0x80
#define UPD_AUTO 0x40
/*I2C Port-0 (PB4,PB5) Control Register*/
extern xdata unsigned char IIC0_CFG;
#define PRENACK 0x80
#define SEND_ACK 0x40
#define STOP 0x20
#define RESTART 0x10
#define IIC_400K 0x0c
#define IIC_200K 0x08
#define IIC_100K 0x04
#define IIC_50K 0x00
#define MASTER 0x02
#define WAIT_GEN 0x01
extern xdata unsigned char IIC0_STATUS;
#define DOWRITE 0x80
#define DOREAD 0x40
#define TXIN_NULL 0x20
#define TX_NULL 0x10
#define RXIN_FULL 0x08
#define RX_FULL 0x04
#define BUS_START 0x02
#define BUS_STOP 0x01
extern xdata unsigned char IIC0_INT_EN;
extern xdata unsigned char IIC0INT_FLG;
#define INTA 0x80
#define INTTX 0x40
#define INTRX 0x20
#define INTNAK 0x10
#define INTLOST 0x08
#define SEND_START 0x02
#define SEND_STOP 0x01
extern xdata unsigned char IIC0INT_CLR;
#define SET_NO_DATA_IN 0x04
#define CLR_FIFO 0x02
extern xdata unsigned char IIC0_TXDATA;
//extern xdata unsigned char volatile IIC0_RXDATA;
extern xdata unsigned char IIC0_RXDATA;
extern xdata unsigned char IIC0_ADDR;
#define ENIIC 0x01
/*I2C Port-1 (PB6,PB7) Control Register*/
extern xdata unsigned char IIC1_CFG;
extern xdata unsigned char IIC1_STATUS;
extern xdata unsigned char IIC1_INT_EN;
extern xdata unsigned char IIC1INT_FLG;
extern xdata unsigned char IIC1INT_CLR;
extern xdata unsigned char IIC1_TXDATA;
extern xdata unsigned char IIC1_RXDATA;
extern xdata unsigned char IIC1_ADDR;
/* Flash Memory */
extern xdata unsigned char ISP_REG;
#define ISP_FLG 0x02
#define ISP_CH 0x01
extern xdata unsigned char FLASH_BUF;
extern xdata unsigned char DDCPtr0; // (R/W) : $07
extern xdata unsigned char DDCPtr1; // (R/W) : $07
#endif
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