📄 rc500.lst
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707 ///////////////////////////////////////////////////////////////////////
708 // M I F A R E M O D U L E R E S E T
709 ///////////////////////////////////////////////////////////////////////
710 char M500PcdReset(void)
711 {
712 1 char idata status = MI_OK;
713 1 RC500RST = 0; // clear reset pin
714 1 delay_1ms(25); // wait for 25ms
715 1 RC500RST = 1; // reset RC500
716 1 delay_50us(50); // wait for 2.5ms
717 1 RC500RST = 0; // clear reset pin
718 1
719 1 start_timeout(42000); // count down with a period of 50 us
720 1 // 42000 * 50 us = 2.1 s
721 1
722 1 // wait until reset command recognized
723 1
724 1 while (((ReadRawIO(RegCommand) & 0x3F) != 0x3F) && !T2IR)TOGGLE_WD();
725 1 // while reset sequence in progress
726 1 while ((ReadRawIO(RegCommand) & 0x3F) && !T2IR) TOGGLE_WD();
727 1 // i=RegCommand;
728 1 // status=ReadRawIO(i);
729 1 // status=status&0x3f;
730 1
731 1 stop_timeout(); // stop timeout counter
732 1
733 1 if (T2IR) // If reader timeout occurs
734 1 {
735 2 status = MI_RESETERR; // respose of reader IC is not correct
736 2 T2IR = 0;
C51 COMPILER V7.20 RC500 02/04/2007 10:44:17 PAGE 13
737 2 }
738 1 else
739 1 {
740 2 WriteRawIO(RegPage,0x80); // Dummy access in order to determine the bus
741 2 // configuration
742 2 // necessary read access
743 2 // after first write access, the returned value
744 2 // should be zero ==> interface recognized
745 2
746 2 if (ReadRawIO(RegCommand) != 0x00)
747 2 {
748 3 status = MI_INTERFACEERR;
749 3 }
750 2 WriteRawIO(RegPage,0x00); // configure to linear address mode
751 2
752 2 }
753 1 TOGGLE_WD();
754 1 return status;
755 1 }
756
757 ///////////////////////////////////////////////////////////////////////
758 // M I F A R E M O D U L E C O N F I G U R A T I O N
759 ///////////////////////////////////////////////////////////////////////
760 char M500PcdConfig(void)
761 {
762 1 char idata status;
763 1 // char idata i;//pan dele
764 1 // char idata j;//pan dele
765 1 TOGGLE_WD();
766 1 if ((status = M500PcdReset()) == MI_OK)
767 1 {
768 2 // test clock Q calibration - value in the range of 0x46 expected
769 2 WriteIO(RegClockQControl,0x0);
770 2 WriteIO(RegClockQControl,0x40);
771 2 delay_50us(2); // wait approximately 100 us - calibration in progress
772 2 ClearBitMask(RegClockQControl,0x40); // clear bit ClkQCalib for
773 2 // further calibration
774 2
775 2 // The following values for RegBitPhase and
776 2 // RegRxThreshold represents an optimal
777 2 // value for our demo package. For user
778 2 // implementation some changes could be
779 2 // necessary
780 2 // initialize bit phase
781 2 WriteIO(RegBitPhase,0xAD);
782 2
783 2 // initialize minlevel
784 2 WriteIO(RegRxThreshold,0xFF);
785 2
786 2 // disable auto power down
787 2 WriteIO(RegRxControl2,0x01);
788 2
789 2 // Depending on the processing speed of the
790 2 // operation environment, the waterlevel
791 2 // can be adapted. (not very critical for
792 2 // mifare applications)
793 2 // initialize waterlevel to value 4
794 2 WriteIO(RegFIFOLevel,0x04);
795 2
796 2 //Timer configuration
797 2 WriteIO(RegTimerControl,0x02); // TStopRxEnd=0,TStopRxBeg=0,
798 2 // TStartTxEnd=1,TStartTxBeg=0
C51 COMPILER V7.20 RC500 02/04/2007 10:44:17 PAGE 14
799 2 // timer must be stopped manually
800 2 M500PcdSetTmo(1); // short timeout
801 2
802 2 WriteIO(RegIRqPinConfig,0x03); // interrupt active low enable
803 2
804 2 M500PcdRfReset(1); // Rf - reset and enable output driver
805 2 TOGGLE_WD();
806 2
807 2 }
808 1 TOGGLE_WD();
809 1 return status;
810 1 }
811
812 ///////////////////////////////////////////////////////////////////////
813 // M I F A R E R E M O T E A N T E N N A
814 // Configuration of slave module
815 ///////////////////////////////////////////////////////////////////////
816 /*char M500PcdMfInOutSlaveConfig(void)
817 {
818 char idata status = MI_OK;
819
820 FlushFIFO(); // empty FIFO
821 ResetInfo(MInfo);
822 MSndBuffer[0] = 0x10; // addr low byte
823 MSndBuffer[1] = 0x00; // addr high byte
824
825 MSndBuffer[2] = 0x00; // Page
826 MSndBuffer[3] = 0x7B; // RegTxControl modsource 11,InvTx2,Tx2RFEn,TX1RFEn
827 MSndBuffer[4] = 0x3F; // RegCwConductance
828 MSndBuffer[5] = 0x3F; // RFU13
829 MSndBuffer[6] = 0x19; // RFU14
830 MSndBuffer[7] = 0x13; // RegModWidth
831 MSndBuffer[8] = 0x00; // RFU16
832 MSndBuffer[9] = 0x00; // RFU17
833
834 MSndBuffer[10] = 0x00; // Page
835 MSndBuffer[11] = 0x73; // RegRxControl1
836 MSndBuffer[12] = 0x08; // RegDecoderControl
837 MSndBuffer[13] = 0x6c; // RegBitPhase
838 MSndBuffer[14] = 0xFF; // RegRxThreshold
839 MSndBuffer[15] = 0x00; // RFU1D
840 MSndBuffer[16] = 0x00; // RegRxControl2
841 MSndBuffer[17] = 0x00; // RegClockQControl
842
843 MSndBuffer[18] = 0x00; // Page
844 MSndBuffer[19] = 0x06; // RegRxWait
845 MSndBuffer[20] = 0x03; // RegChannelRedundancy
846 MSndBuffer[21] = 0x63; // RegCRCPresetLSB
847 MSndBuffer[22] = 0x63; // RegCRCPresetMSB
848 MSndBuffer[23] = 0x0; // RFU25
849 MSndBuffer[24] = 0x04; // RegMfOutSelect enable mfout = manchester HT
850 MSndBuffer[25] = 0x00; // RFU27
851
852 // PAGE 5 FIFO, Timer and IRQ-Pin Configuration
853 MSndBuffer[26] = 0x00; // Page
854 MSndBuffer[27] = 0x08; // RegFIFOLevel
855 MSndBuffer[28] = 0x07; // RegTimerClock
856 MSndBuffer[29] = 0x06; // RegTimerControl
857 MSndBuffer[30] = 0x0A; // RegTimerReload
858 MSndBuffer[31] = 0x02; // RegIRqPinConfig
859 MSndBuffer[32] = 0x00; // RFU
860 MSndBuffer[33] = 0x00; // RFU
C51 COMPILER V7.20 RC500 02/04/2007 10:44:17 PAGE 15
861 MInfo.nBytesToSend = 34;
862
863 status = M500PcdCmd(PCD_WRITEE2,
864 MSndBuffer,
865 MRcvBuffer,
866 &MInfo); // write e2
867 return status;
868 }
869 */
870 ///////////////////////////////////////////////////////////////////////
871 // M I F A R E R E M O T E A N T E N N A
872 // Configuration of master module
873 ///////////////////////////////////////////////////////////////////////
874 char M500PcdMfInOutMasterConfig(void)
875 {
876 1 WriteIO(RegRxControl2,0x42);
877 1 WriteIO(RegTxControl,0x10);
878 1 WriteIO(RegBitPhase,0x11);
879 1 TOGGLE_WD();
880 1 return MI_OK;
881 1 }
882 ///////////////////////////////////////////////////////////////////////
883 // E E P R O M R E A D
884 ///////////////////////////////////////////////////////////////////////
885 char PcdReadE2(unsigned short startaddr,
886 unsigned char length,
887 unsigned char* _data)
888 {
889 1 char status = MI_OK;
890 1 TOGGLE_WD();
891 1 // ************* Cmd Sequence **********************************
892 1 ResetInfo(MInfo);
893 1 MSndBuffer[0] = startaddr & 0xFF;
894 1 MSndBuffer[1] = (startaddr >> 8) & 0xFF;
895 1 MSndBuffer[2] = length;
896 1 MInfo.nBytesToSend = 3;
897 1 status = M500PcdCmd(PCD_READE2,
898 1 MSndBuffer,
899 1 MRcvBuffer,
900 1 &MInfo);
901 1 if (status == MI_OK)
902 1 {
903 2 memcpy(_data,MRcvBuffer,length);
904 2 }
905 1 else // Response Processing
906 1 {
907 2 _data[0] = 0;
908 2 }
909 1 TOGGLE_WD();
910 1 return status ;
911 1 }
912
913 ///////////////////////////////////////////////////////////////////////
914 // E E P R O M W R I T E
915 ///////////////////////////////////////////////////////////////////////
916 char PcdWriteE2(unsigned short startaddr,
917 unsigned char length,
918 unsigned char* _data)
919 {
920 1 char status = MI_OK;
921 1 TOGGLE_WD();
922 1 // ************* Cmd Sequence **********************************
C51 COMPILER V7.20 RC500 02/04/2007 10:44:17 PAGE 16
923 1 ResetInfo(MInfo);
924 1 MSndBuffer[0] = startaddr & 0xFF;
925 1 MSndBuffer[1] = (startaddr >> 8) & 0xFF;
926 1 memcpy(MSndBuffer + 2,_data,length);
927 1
928 1 MInfo.nBytesToSend = length + 2;
929 1
930 1 status = M500PcdCmd(PCD_WRITEE2,
931 1 MSndBuffer,
932 1 MRcvBuffer,
933 1 &MInfo); // write e2
934 1 TOGGLE_WD();
935 1 return status;
936 1 }
937
938 ///////////////////////////////////////////////////////////////////////
939 // C O N F I G M F O U T S E L E C T
940 ///////////////////////////////////////////////////////////////////////
941 char M500PcdMfOutSelect(unsigned char type)
942 {
943 1 WriteIO(RegMfOutSelect,type&0x7);
944 1 TOGGLE_WD();
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